[EMAIL PROTECTED] removed from CC since I can't post to it. Jon Smirl writes:
> It shouldn't hurt to have a parallel non-cached mapping being used in > conjuction with this protocol. By definition the non-cached mapping > never gets into an inconsistent state. According to the PowerPC Architecture specification, it is a programming error to have both cacheable and uncacheable mappings of the same page. That means the hardware designers consider that they don't have to worry if the hardware misbehaves if software does that. :P So that is not a feasible solution for us. Paul. ------------------------------------------------------- SF email is sponsored by - The IT Product Guide Read honest & candid reviews on hundreds of IT Products from real users. Discover which products truly live up to the hype. Start reading now. http://ads.osdn.com/?ad_id=6595&alloc_id=14396&op=click -- _______________________________________________ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
