Hi !

The radeon DRM has some interesting bug that paul and I discovered to
cause all sort of problems like crashing the machine on suspend/resume
(go figure ...) etc...

        dev_priv->gart_vm_start = dev_priv->fb_location
                                + RADEON_READ( RADEON_CONFIG_APER_SIZE );

The "aim" of this code is to setup the card memory map so that the GART
sits just after the framebuffer. However, CONFIG_APER_SIZE is _not_ a
good indication of the framebuffer size.

CONFIG_APER_SIZE is only the size of the visible aperture on the PCI
bus. Some setups (like some Macs for example) can use the dual split
aperture mecanism, in which case CONFIG_APER_SIZE is only half of the
VRAM. I can imagine cards overloaded with memory to have more vram that
is directly accessible from PCI in other circumstances too (though the
split aperture case is a real world scenario we encountered on paul's
laptop at least).

The result is we end up putting the GART right in the middle of VRAM in
card's space. The card's memory controller at best does nothing of it,
at worst blows up in funny way when the engine is reset, or in some
case, when re-initializing from suspend/resume cycle.

In practice, you are setting up the card's memory map, so
CONFIG_APER_SIZE should be totally irrelevant anyway since it only
affects the PCI window to the vram. What is relevant here is
CONFIG_MEMSIZE I would say...

        dev_priv->gart_vm_start = dev_priv->fb_location
                                + RADEON_READ( RADEON_CONFIG_MEMSIZE );

If we want to be totally paranoid, we may want to use the max of CONFIG_MEMSIZE
and CONFIG_APER_SIZE (to avoid leaving part of the GART mapped though the
PCI aperture.

Note that with huge VRAM sizes appearing, we also want to make sure that
wheverver we put it won't overlap the 32 bits space since CONFIG_MEM_SIZE
can be huge nowadays... and if it does, put the GART just _before_ the
framebuffer instead. Again, this is all cards space, not bus view, so that
shouldn't matter where we put these things.

Cheers,
Ben.




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