On Tue, 2007-11-27 at 07:17 +0800, 郭超洪 wrote: > > /* TODO: Fix this more elegantly. > * Sometimes (especially with multiple DRI clients), this code > * runs immediately after a DRI client issues a rendering command. > * > * The accel code regularly inserts WAIT_UNTIL_IDLE into the > * command buffer that is sent with the indirect buffer below. > * The accel code fails to set the 3D cache flush registers for > * the R300 before sending WAIT_UNTIL_IDLE. Sending a cache flush > * on these new registers is not necessary for pure 2D functionality, > * but it *is* necessary after 3D operations. > * Without the cache flushes before WAIT_UNTIL_IDLE, the R300 locks up. > * > * The CP_IDLE call into the DRM indirectly flushes all caches and > * thus avoids the lockup problem, but the solution is far from ideal. > * Better solutions could be: > * - always flush caches when entering the X server > * - track the type of rendering commands somewhere and issue > * cache flushes when they change > * However, I don't feel confident enough with the control flow > * inside the X server to implement either fix. -- nh > > if (info->ChipFamily>=CHIP_FAMILY_R300) > drmCommandNone(info->drmFD, DRM_RADEON_CP_IDLE); > }
This code is gone in current xf86-video-ati; grep it for info->needCacheFlush. -- Earthling Michel Dänzer | http://tungstengraphics.com Libre software enthusiast | Debian, X and DRI developer ------------------------------------------------------------------------- This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2005. http://clk.atdmt.com/MRT/go/vse0120000070mrt/direct/01/ -- _______________________________________________ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
