The GWB flush BAR for i915 and later chipsets is 64-bits wide, but on 32-bit kernels, the resources are 32-bits. Use the upper_32_bits macro instead of a shift by 32 to extract the right value on all machines.
diff --git a/linux-core/i915_compat.c b/linux-core/i915_compat.c
index e119a99..f03f6c7 100644
--- a/linux-core/i915_compat.c
+++ b/linux-core/i915_compat.c
@@ -84,7 +84,7 @@ static void intel_i965_g33_setup_chipset_flush(struct pci_dev
*pdev)
intel_alloc_chipset_flush_resource(pdev);
- pci_write_config_dword(pdev, I965_IFPADDR + 4,
(i9xx_private.ifp_resource.start >> 32));
+ pci_write_config_dword(pdev, I965_IFPADDR + 4, upper_32_bits
(i9xx_private.ifp_resource.start));
pci_write_config_dword(pdev, I965_IFPADDR,
(i9xx_private.ifp_resource.start & 0xffffffff) | 0x1);
} else {
u64 l64;
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