http://bugs.freedesktop.org/show_bug.cgi?id=15472
--- Comment #2 from Jie Luo <[EMAIL PROTECTED]> 2008-04-14 01:11:01 PST --- After reading the graphic core document from intel video driver site. I did some debug. Here is the result of dump debug register. This is the regdump of normal state. IPEIR: 0 IPEHR: 0 EIR: 0 ESR: 0 EMR: 0xffff INSTDONE: 0xffc0 INSTPM: 0 MEMMODE: 0x306 INSTPS: 0xf0000 HWSTAM: 0xfffe IER: 0x2 IMR: 0 IIR: 0x20 This is the regdump of the state ESR being set to 0x00000001. IPEIR: 0 IPEHR: 0 EIR: 0 ESR: 0x1 EMR: 0xffff INSTDONE: 0xffc0 INSTPM: 0 MEMMODE: 0x306 INSTPS: 0xf0000 HWSTAM: 0xfffe IER: 0xa2 IMR: 0 IIR: 0x50 According to the document, ESR being set to 0x1 indicate Instruction Error. The document said that IPEHR register contains the header (DWord 0) of the faulting instruction. So the faulting instruction is a MI instruction. IER being set to be 0xa2 means 'Display Plane C Flip Pending' and 'Display Pipe B VBLANK' is enabled. But because I don't have a PIPE C, this means the Instruction Error is caused by a MI_DISPLAY_BUFFER_INFO instruction with a defeatured opcode (PIPE C). Any comments? -- Configure bugmail: http://bugs.freedesktop.org/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are the assignee for the bug. ------------------------------------------------------------------------- This SF.net email is sponsored by the 2008 JavaOne(SM) Conference Don't miss this year's exciting event. There's still time to save $100. Use priority code J8TL2D2. http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone -- _______________________________________________ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
