On Wed, 2008-11-05 at 16:49 -0800, Jesse Barnes wrote: > Use the new core GEM object mapping code to allow GTT mapping of GEM objects > on i915. The fault handler will make sure a fence register is allocated too, > if the object in question is tiled.
I required the following patch on top of your change to get it compiling
on non-x86_64. Also the args to the gtt mmap ioctl should be cut to
what's actually used. (or, imo, make it actually do the map on the
device's filp, like the other mmap ioctl does :) )
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3a7e2bb..3495117 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -585,11 +585,17 @@ static inline void opregion_enable_asle(struct drm_device
*dev) { return; }
#define I915_READ(reg) readl(dev_priv->regs + (reg))
#define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
-#define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
#define I915_READ16(reg) readw(dev_priv->regs + (reg))
#define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
#define I915_READ8(reg) readb(dev_priv->regs + (reg))
#define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
+#ifdef writeq
+#define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
+#else
+#define I915_WRITE64(reg, val) (writel(val, dev_priv->regs + (reg)), \
+ writel(upper_32_bits(val), \
+ dev_priv->regs + (reg) + 4))
+#endif
#define I915_VERBOSE 0
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d5c909a..98f6f49 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1395,8 +1395,8 @@ static void i965_write_fence_reg(struct
drm_i915_fence_reg *reg)
int regnum = obj_priv->fence_reg;
uint64_t val;
- val = ((obj_priv->gtt_offset + obj->size - 4096) &
- 0xfffff000) << 32;
+ val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
+ 0xfffff000) << 32;
val |= obj_priv->gtt_offset & 0xfffff000;
val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
if (obj_priv->tiling_mode == I915_TILING_Y)
--
Eric Anholt
[EMAIL PROTECTED] [EMAIL PROTECTED]
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