[please cc me directly, as i dont subscribe to this list, thanks!]
i am trying to get drm from 2.6.27 and x11r7.4 working on my sn2 (ia64)
system in order to support an ati firegl graphics card. it works fine
on my amd64 system running in 64-bit mode. however, on the sn2 i get a
new address/bus fault. i believe my problem comes from the pci mapping
of the cards address space. on the 64-bit amd box:
07:00.0 VGA compatible controller: ATI Technologies Inc Unknown device 710e
(prog-if 00 [VGA controller])
Subsystem: ATI Technologies Inc Unknown device 0b32
Flags: bus master, fast devsel, latency 0, IRQ 146
Memory at c0000000 (64-bit, prefetchable) [size=256M]
Memory at dfff0000 (64-bit, non-prefetchable) [size=64K]
I/O ports at d000 [size=256]
Expansion ROM at dffc0000 [disabled] [size=128K]
Capabilities: [50] Power Management version 2
Capabilities: [58] Express Endpoint IRQ 0
Capabilities: [80] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0
Enable-
note that despite the machine being 64-bit, the location for bar0
is in the lower 2G of memory. on the sn2 machine:
0053:02:00.0 VGA compatible controller: ATI Technologies Inc Unknown device
710f (prog-if 00 [VGA controller])
Subsystem: ATI Technologies Inc Unknown device 0b32
Flags: bus master, fast devsel, latency 0, IRQ 69
Memory at 98210000000 (64-bit, prefetchable) [size=256M]
Memory at 98200100000 (64-bit, non-prefetchable) [size=64K]
I/O ports at 1000 [size=256]
Expansion ROM at c0003f69ee934000 [disabled] [size=61K]
Capabilities: [50] Power Management version 2
Capabilities: [58] Express Endpoint IRQ 0
Capabilities: [80] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0
Enable-
you will note that bar0 is (well) above the 2G address line. right before
the crash on the ia64, i see the following with drm debugging enabled:
[drm:radeon_do_init_cp] Setting phys_pci_gart to c00009821fffe000
0FFFE000
[drm:drm_ati_pcigart_init] PCI: Gart Table: VRAM 0FFFE000 mapped at
C00009821FFFE000
this seems bad. i dont think the vram for this card is located at this memory
address. on the amd64 machine, i see the following:
[drm:radeon_do_init_cp] Setting phys_pci_gart to ffffc2000a0b0000
0FFF8000
[drm:drm_ati_pcigart_init] PCI: Gart Table: VRAM CFFF8000 mapped at
FFFFC2000A0B0000
this seems correct to me (and indeed the radeon driver works fine on
the am64 machine). it appears that the gart table/bus address for
the card is derived from the pcigart_offset:
if (dev_priv->pcigart_offset_set) {
dev_priv->gart_info.bus_addr =
dev_priv->pcigart_offset + dev_priv->fb_location;
and the pcigart_offset is set from the userspace radeon dri driver
via RADEON_SETPARAM_PCIGART_LOCATION which passes a 32-bit value up to
the kernel. it appears that the pciGartOffset in the userspace driver
is computed as a 32-bit value as well.
am i correct in my understanding and if so, how should this be fixed?
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