On Friday, January 23, 2009 2:08 pm Jesse Barnes wrote:
> With DRI2 and UXA we don't actually tile back, depth or fake front buffers
> like we should on pre-965 chips, since they require fence regs to be set up
> in order to render properly.
>
> This patchset re-adds basic support for tiled rendering on pre-965 in some
> configurations. It's been lightly tested on 915GM and 945GM so far,
> additional testing is welcome. It seems to make a good difference on most
> 3D rendering, but doesn't quite bring it back up to DRI1 levels, so more
> optimization is still needed. It also won't work on machines with the bit
> 17 XOR randomization applied, since the swizzling in that configuration
> isn't supported yet.
Here's what I've been using to see the regs with intel_reg_dumper.
--
Jesse Barnes, Intel Open Source Technology Center
diff --git a/src/i810_reg.h b/src/i810_reg.h
index e2ffba1..75f3c9b 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -563,7 +563,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define FENCE_XMAJOR 1
#define FENCE_YMAJOR 2
-#define I915G_FENCE_START_MASK 0x0ff00000
+#define I915G_FENCE_START_MASK 0x1ff00000
#define I830_FENCE_START_MASK 0x07f80000
diff --git a/src/i830.h b/src/i830.h
index 4794169..f9444b1 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -969,6 +969,7 @@ i830_get_transformed_coordinates_3d(int x, int y, PictTransformPtr transform,
float *x_out, float *y_out, float *z_out);
void i830_enter_render(ScrnInfoPtr);
+unsigned long I830GetFencePitch(I830Ptr pI830, unsigned long pitch, int format);
static inline void
i830_wait_ring_idle(ScrnInfoPtr pScrn)
------------------------------------------------------------------------------
This SF.net email is sponsored by:
SourcForge Community
SourceForge wants to tell your story.
http://p.sf.net/sfu/sf-spreadtheword
--
_______________________________________________
Dri-devel mailing list
Dri-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/dri-devel
