On Wed, 28 Jan 2009 11:30:53 +0000 (GMT) Dave Airlie <airl...@linux.ie> wrote: > Good point, the attached fixes that. it looks more proper! > Yes it should be fine, write combining shouldn't re-order, > and its been write combined using an mtrr for years. WC has weak-ordering. For FrameBuffer data, correctness isn't so important.
I realize ring buffer is used to with drm syncing. prove unfounded. On Wed, 28 Jan 2009 13:40:29 +0100 Michel Dänzer <mic...@daenzer.net> wrote: > Yeah, we were over this years ago. :) The radeon COMMIT_RING() macro > takes care of this: > > /* Flush writes to ring */ \ > DRM_MEMORYBARRIER(); \ > GET_RING_HEAD( dev_priv ); \ > RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \ > /* read from PCI bus to ensure correct posting */ \ > RADEON_READ( RADEON_CP_RB_RPTR ); \ > ------------------------------------------------------------------------------ This SF.net email is sponsored by: SourcForge Community SourceForge wants to tell your story. http://p.sf.net/sfu/sf-spreadtheword -- _______________________________________________ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
