From: Benjamin Herrenschmidt <b...@kernel.crashing.org> Date: Sat, 14 Feb 2009 20:07:54 +1100
> > I did some research, and it does appear that the GART does read the > > PTEs from the VRAM using the Host Data Path. This means the surface > > control byte swapping settings are applied. > > > > So for depths of 16 and 24, the GART is reading garbage PTEs. And > > that's why the CP hangs. > > That makes me wonder how the heck did it work for me ! Or maybe... I've > been using an R5xx which happens to have a bit that I haven't seen on > R3xx that allows ... to set whether the GART reads come from HDP or > directly from MC. That might be what saved my ass here. I wonder. But I really doubt it. The bit is off by default and the radeon DRM code explicitly sets it to off. > We can do that by registering a surface from the kernel to cover the > GART I suppose, and clean things a bit so that when using the DRI, X > doesn't touch the surface registers -at all- and leaves it to the > kernel. That actually sounds like a good idea. ------------------------------------------------------------------------------ Open Source Business Conference (OSBC), March 24-25, 2009, San Francisco, CA -OSBC tackles the biggest issue in open source: Open Sourcing the Enterprise -Strategies to boost innovation and cut costs with open source participation -Receive a $600 discount off the registration fee with the source code: SFAD http://p.sf.net/sfu/XcvMzF8H -- _______________________________________________ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
