The calculations are wrong.
E.g. for image 16 x 16, format is DXT3 (block size = 16 bytes, block width =
4, block height = 4) the size is 256. Yours code would calculate it as 16 *
(16 / 4) = 64.
The proper way to calculate it is
unsigned wblocks = (width + blockWidth - 1) / blockWidth;
unsigned hblocks = (height + blockHeight - 1) / blockHeight;
unsigned size = wblocks * hblocks * bytesPerBlock;
For DXT1 blockWidth is 4, blockHeight 4 and bytesPerBlock 4.
For DXT3 and DXT5 blockWidth is 4, blockHeight 4 and bytesPerBlock 8.
For small textures wblocks need to be aligned to 4 for DXT1, and 2 for DXT3/5
You may want to look at get_compressed_image_size in radeon_mipmap_tree.c and
_mesa_format_image_size in mesa/src/mesa/main/formats.c for reference.
Regards,
Maciej
Dnia poniedziałek, 7 grudnia 2009 o 04:17:52 Dave Airlie napisał(a):
> From: Dave Airlie <airl...@redhat.com>
>
> This adds support for compressed textures to the r100->r500 CS
> checker, it lets me run openarena and the demos in mesa fine,
> If someone can check the size calcs for DXT1/35 the w//h changes
> that would be nice.
>
> Signed-off-by: Dave Airlie <airl...@redhat.com>
> ---
> drivers/gpu/drm/radeon/r100.c | 26 +++++++++++++++++++++++---
> drivers/gpu/drm/radeon/r100_track.h | 5 +++++
> drivers/gpu/drm/radeon/r200.c | 10 ++++++++--
> drivers/gpu/drm/radeon/r300.c | 12 +++++++++---
> 4 files changed, 45 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
> index 79206e9..6597b5c 100644
> --- a/drivers/gpu/drm/radeon/r100.c
> +++ b/drivers/gpu/drm/radeon/r100.c
> @@ -1256,7 +1256,6 @@ static int r100_packet0_check(struct radeon_cs_parser
> *p, case RADEON_TXFORMAT_ARGB4444:
> case RADEON_TXFORMAT_VYUY422:
> case RADEON_TXFORMAT_YVYU422:
> - case RADEON_TXFORMAT_DXT1:
> case RADEON_TXFORMAT_SHADOW16:
> case RADEON_TXFORMAT_LDUDV655:
> case RADEON_TXFORMAT_DUDV88:
> @@ -1264,12 +1263,19 @@ static int r100_packet0_check(struct
> radeon_cs_parser *p, break;
> case RADEON_TXFORMAT_ARGB8888:
> case RADEON_TXFORMAT_RGBA8888:
> - case RADEON_TXFORMAT_DXT23:
> - case RADEON_TXFORMAT_DXT45:
> case RADEON_TXFORMAT_SHADOW32:
> case RADEON_TXFORMAT_LDUDUV8888:
> track->textures[i].cpp = 4;
> break;
> + case RADEON_TXFORMAT_DXT1:
> + track->textures[i].cpp = 1;
> + track->textures[i].compress_format =
> R100_TRACK_COMP_DXT1;
> + break;
> + case RADEON_TXFORMAT_DXT23:
> + case RADEON_TXFORMAT_DXT45:
> + track->textures[i].cpp = 1;
> + track->textures[i].compress_format =
> R100_TRACK_COMP_DXT35;
> + break;
> }
> track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16)
> & 0xf);
> track->textures[i].cube_info[4].height = 1 << ((idx_value >>
> 20) & 0xf);
> @@ -2588,6 +2594,7 @@ static inline void r100_cs_track_texture_print(struct
> r100_cs_track_texture *t) DRM_ERROR("coordinate type %d\n",
> t->tex_coord_type); DRM_ERROR("width round to power of 2 %d\n",
> t->roundup_w);
> DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
> + DRM_ERROR("compress format %d\n", t->compress_format);
> }
>
> static int r100_cs_track_cube(struct radeon_device *rdev,
> @@ -2654,9 +2661,21 @@ static int r100_cs_track_texture_check(struct
> radeon_device *rdev, h = h / (1 << i);
> if (track->textures[u].roundup_h)
> h = roundup_pow_of_two(h);
> + if (track->textures[u].compress_format) {
> + /* compressed textures are block based */
> + if (track->textures[u].compress_format ==
> R100_TRACK_COMP_DXT1) {
> + w *= 2;
> + h /= 8;
> + } else {
> + h /= 4;
> + }
> + if (w < 32)
> + w = 32;
> + }
> size += w * h;
> }
> size *= track->textures[u].cpp;
> +
> switch (track->textures[u].tex_coord_type) {
> case 0:
> break;
> @@ -2821,6 +2840,7 @@ void r100_cs_track_clear(struct radeon_device *rdev,
> struct r100_cs_track *track track->arrays[i].esize = 0x7F;
> }
> for (i = 0; i < track->num_texture; i++) {
> + track->textures[i].compress_format = R100_TRACK_COMP_NONE;
> track->textures[i].pitch = 16536;
> track->textures[i].width = 16536;
> track->textures[i].height = 16536;
> diff --git a/drivers/gpu/drm/radeon/r100_track.h
> b/drivers/gpu/drm/radeon/r100_track.h index 0daf0d7..c3eaba5 100644
> --- a/drivers/gpu/drm/radeon/r100_track.h
> +++ b/drivers/gpu/drm/radeon/r100_track.h
> @@ -28,6 +28,10 @@ struct r100_cs_cube_info {
> unsigned height;
> };
>
> +#define R100_TRACK_COMP_NONE 0
> +#define R100_TRACK_COMP_DXT1 1
> +#define R100_TRACK_COMP_DXT35 2
> +
> struct r100_cs_track_texture {
> struct radeon_object *robj;
> struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces
> */
> @@ -44,6 +48,7 @@ struct r100_cs_track_texture {
> bool enabled;
> bool roundup_w;
> bool roundup_h;
> + unsigned compress_format;
> };
>
> struct r100_cs_track_limits {
> diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c
> index eb740fc..2094212 100644
> --- a/drivers/gpu/drm/radeon/r200.c
> +++ b/drivers/gpu/drm/radeon/r200.c
> @@ -401,7 +401,6 @@ int r200_packet0_check(struct radeon_cs_parser *p,
> case R200_TXFORMAT_Y8:
> track->textures[i].cpp = 1;
> break;
> - case R200_TXFORMAT_DXT1:
> case R200_TXFORMAT_AI88:
> case R200_TXFORMAT_ARGB1555:
> case R200_TXFORMAT_RGB565:
> @@ -418,9 +417,16 @@ int r200_packet0_check(struct radeon_cs_parser *p,
> case R200_TXFORMAT_ABGR8888:
> case R200_TXFORMAT_BGR111110:
> case R200_TXFORMAT_LDVDU8888:
> + track->textures[i].cpp = 4;
> + break;
> + case R200_TXFORMAT_DXT1:
> + track->textures[i].cpp = 1;
> + track->textures[i].compress_format =
> R100_TRACK_COMP_DXT1;
> + break;
> case R200_TXFORMAT_DXT23:
> case R200_TXFORMAT_DXT45:
> - track->textures[i].cpp = 4;
> + track->textures[i].cpp = 1;
> + track->textures[i].compress_format =
> R100_TRACK_COMP_DXT1;
> break;
> }
> track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16)
> & 0xf);
> diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
> index 430fc2a..828f8ad 100644
> --- a/drivers/gpu/drm/radeon/r300.c
> +++ b/drivers/gpu/drm/radeon/r300.c
> @@ -847,7 +847,6 @@ static int r300_packet0_check(struct radeon_cs_parser
> *p, case R300_TX_FORMAT_Z6Y5X5:
> case R300_TX_FORMAT_W4Z4Y4X4:
> case R300_TX_FORMAT_W1Z5Y5X5:
> - case R300_TX_FORMAT_DXT1:
> case R300_TX_FORMAT_D3DMFT_CxV8U8:
> case R300_TX_FORMAT_B8G8_B8G8:
> case R300_TX_FORMAT_G8R8_G8B8:
> @@ -861,8 +860,6 @@ static int r300_packet0_check(struct radeon_cs_parser
> *p, case 0x17:
> case R300_TX_FORMAT_FL_I32:
> case 0x1e:
> - case R300_TX_FORMAT_DXT3:
> - case R300_TX_FORMAT_DXT5:
> track->textures[i].cpp = 4;
> break;
> case R300_TX_FORMAT_W16Z16Y16X16:
> @@ -873,6 +870,15 @@ static int r300_packet0_check(struct radeon_cs_parser
> *p, case R300_TX_FORMAT_FL_R32G32B32A32:
> track->textures[i].cpp = 16;
> break;
> + case R300_TX_FORMAT_DXT1:
> + track->textures[i].cpp = 1;
> + track->textures[i].compress_format =
> R100_TRACK_COMP_DXT1;
> + break;
> + case R300_TX_FORMAT_DXT3:
> + case R300_TX_FORMAT_DXT5:
> + track->textures[i].cpp = 1;
> + track->textures[i].compress_format =
> R100_TRACK_COMP_DXT35;
> + break;
> default:
> DRM_ERROR("Invalid texture format %u\n",
> (idx_value & 0x1F));
>
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