This patch simplify the GPU address space initialization, it always try to put VRAM at same address as the CPU PCI aperture for the VRAM. Sadly it seems that the memory controller of radeon got too many bugs to safely put it at others place (especialy on IGP).
This patch also kill some duplicated value and split vram size into 2 different value the mc_vram_size which will always be the true VRAM size of the GPU, while vram_size is the amount of VRAM we will use (it can be less than mc_vram_size if we limit the VRAM size or for matching the aperture size). This cleanup is done as first pass before adding support for unmapped VRAM. Signed-off-by: Jerome Glisse <[email protected]> --- drivers/gpu/drm/radeon/r100.c | 51 +++++-------- drivers/gpu/drm/radeon/r300.c | 6 +- drivers/gpu/drm/radeon/r420.c | 6 +- drivers/gpu/drm/radeon/r520.c | 2 +- drivers/gpu/drm/radeon/r600.c | 68 +++-------------- drivers/gpu/drm/radeon/radeon.h | 21 ++++- drivers/gpu/drm/radeon/radeon_device.c | 107 +++++++++++++-------------- drivers/gpu/drm/radeon/radeon_fb.c | 6 +- drivers/gpu/drm/radeon/radeon_gem.c | 4 +- drivers/gpu/drm/radeon/radeon_legacy_crtc.c | 2 +- drivers/gpu/drm/radeon/radeon_test.c | 2 +- drivers/gpu/drm/radeon/radeon_ttm.c | 19 ++--- drivers/gpu/drm/radeon/rs400.c | 9 +- drivers/gpu/drm/radeon/rs600.c | 19 ++--- drivers/gpu/drm/radeon/rs690.c | 19 ++--- drivers/gpu/drm/radeon/rv515.c | 2 +- drivers/gpu/drm/radeon/rv770.c | 48 +++---------- 17 files changed, 150 insertions(+), 241 deletions(-) diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index b7baf16..b9f0e04 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -200,9 +200,8 @@ int r100_pci_gart_enable(struct radeon_device *rdev) tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; WREG32(RADEON_AIC_CNTL, tmp); /* set address range for PCI address translate */ - WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location); - tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; - WREG32(RADEON_AIC_HI_ADDR, tmp); + WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); + WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); /* set PCI GART page-table base address */ WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; @@ -1881,28 +1880,19 @@ void r100_vram_init_sizes(struct radeon_device *rdev) uint32_t tom; /* read NB_TOM to get the amount of ram stolen for the GPU */ tom = RREG32(RADEON_NB_TOM); - rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); + rdev->mc.mc_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); /* for IGPs we need to keep VRAM where it was put by the BIOS */ - rdev->mc.vram_location = (tom & 0xffff) << 16; - WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); - rdev->mc.mc_vram_size = rdev->mc.real_vram_size; + rdev->mc.vram_start = (tom & 0xffff) << 16; + WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.mc_vram_size); } else { - rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); + rdev->mc.mc_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); /* Some production boards of m6 will report 0 * if it's 8 MB */ - if (rdev->mc.real_vram_size == 0) { - rdev->mc.real_vram_size = 8192 * 1024; - WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); - } - /* let driver place VRAM */ - rdev->mc.vram_location = 0xFFFFFFFFUL; - /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - - * Novell bug 204882 + along with lots of ubuntu ones */ - if (config_aper_size > rdev->mc.real_vram_size) - rdev->mc.mc_vram_size = config_aper_size; - else - rdev->mc.mc_vram_size = rdev->mc.real_vram_size; + if (rdev->mc.mc_vram_size == 0) { + rdev->mc.mc_vram_size = 8192 * 1024; + WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.mc_vram_size); + } } /* work out accessible VRAM */ @@ -1913,12 +1903,9 @@ void r100_vram_init_sizes(struct radeon_device *rdev) if (accessible > rdev->mc.aper_size) accessible = rdev->mc.aper_size; - - if (rdev->mc.mc_vram_size > rdev->mc.aper_size) - rdev->mc.mc_vram_size = rdev->mc.aper_size; - - if (rdev->mc.real_vram_size > rdev->mc.aper_size) - rdev->mc.real_vram_size = rdev->mc.aper_size; + rdev->mc.vram_size = accessible; + if (radeon_vram_limit && radeon_vram_limit < rdev->mc.vram_size) + rdev->mc.vram_size = radeon_vram_limit; } void r100_vga_set_state(struct radeon_device *rdev, bool state) @@ -3168,10 +3155,10 @@ void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) { /* Update base address for crtc */ - WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location); + WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); if (!(rdev->flags & RADEON_SINGLE_CRTC)) { WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, - rdev->mc.vram_location); + rdev->mc.vram_start); } /* Restore CRTC registers */ WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); @@ -3335,11 +3322,11 @@ int r100_mc_init(struct radeon_device *rdev) u32 tmp; /* Setup GPU memory space */ - rdev->mc.vram_location = 0xFFFFFFFFUL; - rdev->mc.gtt_location = 0xFFFFFFFFUL; + rdev->mc.vram_start = 0xFFFFFFFFUL; + rdev->mc.gtt_start = 0xFFFFFFFFUL; if (rdev->flags & RADEON_IS_IGP) { tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM)); - rdev->mc.vram_location = tmp << 16; + rdev->mc.vram_start = tmp << 16; } if (rdev->flags & RADEON_IS_AGP) { r = radeon_agp_init(rdev); @@ -3348,7 +3335,7 @@ int r100_mc_init(struct radeon_device *rdev) rdev->flags &= ~RADEON_IS_AGP; rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; } else { - rdev->mc.gtt_location = rdev->mc.agp_base; + rdev->mc.gtt_start = rdev->mc.agp_base; } } r = radeon_mc_setup(rdev); diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index 86065dc..299b4fb 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c @@ -112,15 +112,15 @@ int rv370_pcie_gart_enable(struct radeon_device *rdev) /* discard memory request outside of configured range */ tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); - WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location); - tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - RADEON_GPU_PAGE_SIZE; + WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start); + tmp = rdev->mc.gtt_end + 1 - RADEON_GPU_PAGE_SIZE; WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); table_addr = rdev->gart.table_addr; WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); /* FIXME: setup default page */ - WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_location); + WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); /* Clear error */ WREG32_PCIE(0x18, 0); diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c index 162c390..eafc94a 100644 --- a/drivers/gpu/drm/radeon/r420.c +++ b/drivers/gpu/drm/radeon/r420.c @@ -37,8 +37,8 @@ int r420_mc_init(struct radeon_device *rdev) int r; /* Setup GPU memory space */ - rdev->mc.vram_location = 0xFFFFFFFFUL; - rdev->mc.gtt_location = 0xFFFFFFFFUL; + rdev->mc.vram_start = 0xFFFFFFFFUL; + rdev->mc.gtt_start = 0xFFFFFFFFUL; if (rdev->flags & RADEON_IS_AGP) { r = radeon_agp_init(rdev); if (r) { @@ -46,7 +46,7 @@ int r420_mc_init(struct radeon_device *rdev) rdev->flags &= ~RADEON_IS_AGP; rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; } else { - rdev->mc.gtt_location = rdev->mc.agp_base; + rdev->mc.gtt_start = rdev->mc.agp_base; } } r = radeon_mc_setup(rdev); diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c index 788eef5..7ba0b15 100644 --- a/drivers/gpu/drm/radeon/r520.c +++ b/drivers/gpu/drm/radeon/r520.c @@ -145,7 +145,7 @@ void r520_mc_program(struct radeon_device *rdev) if (r520_mc_wait_for_idle(rdev)) dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); /* Write VRAM size in case we are limiting it */ - WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); + WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.mc_vram_size); /* Program MC, should be a 32bits limited address space */ WREG32_MC(R_000004_MC_FB_LOCATION, S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 6f15090..81c5221 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -657,69 +657,21 @@ int r600_mc_init(struct radeon_device *rdev) rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); /* Setup GPU memory space */ rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); - rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); - - if (rdev->mc.mc_vram_size > rdev->mc.aper_size) - rdev->mc.mc_vram_size = rdev->mc.aper_size; - - if (rdev->mc.real_vram_size > rdev->mc.aper_size) - rdev->mc.real_vram_size = rdev->mc.aper_size; - + rdev->mc.vram_size = rdev->mc.mc_vram_size; + if (rdev->mc.vram_size > rdev->mc.aper_size) + rdev->mc.vram_size = rdev->mc.aper_size; + if (radeon_vram_limit && radeon_vram_limit < rdev->mc.vram_size) + rdev->mc.vram_size = radeon_vram_limit; + rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; if (rdev->flags & RADEON_IS_AGP) { + /* gtt_size is setup by radeon_agp_init */ r = radeon_agp_init(rdev); if (r) return r; - /* gtt_size is setup by radeon_agp_init */ - rdev->mc.gtt_location = rdev->mc.agp_base; - tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; - /* Try to put vram before or after AGP because we - * we want SYSTEM_APERTURE to cover both VRAM and - * AGP so that GPU can catch out of VRAM/AGP access - */ - if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) { - /* Enought place before */ - rdev->mc.vram_location = rdev->mc.gtt_location - - rdev->mc.mc_vram_size; - } else if (tmp > rdev->mc.mc_vram_size) { - /* Enought place after */ - rdev->mc.vram_location = rdev->mc.gtt_location + - rdev->mc.gtt_size; - } else { - /* Try to setup VRAM then AGP might not - * not work on some card - */ - rdev->mc.vram_location = 0x00000000UL; - rdev->mc.gtt_location = rdev->mc.mc_vram_size; - } - } else { - rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; - rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) & - 0xFFFF) << 24; - tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size; - if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { - /* Enough place after vram */ - rdev->mc.gtt_location = tmp; - } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) { - /* Enough place before vram */ - rdev->mc.gtt_location = 0; - } else { - /* Not enough place after or before shrink - * gart size - */ - if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) { - rdev->mc.gtt_location = 0; - rdev->mc.gtt_size = rdev->mc.vram_location; - } else { - rdev->mc.gtt_location = tmp; - rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp; - } - } - rdev->mc.gtt_location = rdev->mc.mc_vram_size; } - rdev->mc.vram_start = rdev->mc.vram_location; - rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; - rdev->mc.gtt_start = rdev->mc.gtt_location; - rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; + r = radeon_mc_setup(rdev); + if (r) + return r; /* FIXME: we should enforce default clock in case GPU is not in * default setup */ diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 5941e7d..53cecd7 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -294,8 +294,21 @@ int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, int pages, struct page **pagelist); -/* - * GPU MC structures, functions & helpers +/** + * struct radeon_mc + * + * @aper_size: vram aperture size + * @aper_base: vram aperture base address in CPU address space + * @mc_vram_size: real vram size (can be > aperture size) + * @gtt_size: gtt size + * @gtt_start: gtt start address in GPU address space + * @gtt_end: gtt end address in GPU address space (start + size - 1) + * @vram_start: vram start address in GPU address space + * @vram_end: vram end address in GPU address space (start + size - 1) + * @vram_width: vram bus size in bits (64bits, 128bits, ...) + * @vram_size: vram reported size always <= mc_vram_size + * @vram_mtrr: mtrr entry covering vram aperture + * @vram_is_ddr: vram is ddr */ struct radeon_mc { resource_size_t aper_size; @@ -304,15 +317,13 @@ struct radeon_mc { /* for some chips with <= 32MB we need to lie * about vram size near mc fb location */ u64 mc_vram_size; - u64 gtt_location; u64 gtt_size; u64 gtt_start; u64 gtt_end; - u64 vram_location; u64 vram_start; u64 vram_end; unsigned vram_width; - u64 real_vram_size; + u64 vram_size; int vram_mtrr; bool vram_is_ddr; }; diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index 410859e..a1160ba 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c @@ -104,71 +104,70 @@ void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) */ int radeon_mc_setup(struct radeon_device *rdev) { - uint32_t tmp; + long tmp; - /* Some chips have an "issue" with the memory controller, the - * location must be aligned to the size. We just align it down, - * too bad if we walk over the top of system memory, we don't - * use DMA without a remapped anyway. - * Affected chips are rv280, all r3xx, and all r4xx, but not IGP - */ - /* FGLRX seems to setup like this, VRAM a 0, then GART. + /* + * VRAM size of more than 2G will likely trigger issue in the + * algorithm we use here. */ + if (rdev->mc.vram_size > 0x80000000UL) + dev_warn(rdev->dev, "VRAM size > 2G, might lead to issue\n"); /* * Note: from R6xx the address space is 40bits but here we only * use 32bits (still have to see a card which would exhaust 4G * address space). */ - if (rdev->mc.vram_location != 0xFFFFFFFFUL) { - /* vram location was already setup try to put gtt after - * if it fits */ - tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size; - tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); - if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { - rdev->mc.gtt_location = tmp; - } else { - if (rdev->mc.gtt_size >= rdev->mc.vram_location) { - printk(KERN_ERR "[drm] GTT too big to fit " - "before or after vram location.\n"); - return -EINVAL; - } - rdev->mc.gtt_location = 0; - } - } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) { - /* gtt location was already setup try to put vram before - * if it fits */ - if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) { - rdev->mc.vram_location = 0; + /* + * Setup address space like this : + * - vram must cover vram aperture (CPU space) + * - gtt after vram if it fits their, otherwise before vram + */ + if ((0xFFFFFFFFUL - rdev->mc.aper_base) > rdev->mc.mc_vram_size) { + rdev->mc.vram_start = rdev->mc.aper_base; + } else { + /* VRAM is to big to fit at aperture base, put vram start + * before so it cover aperture too + */ + tmp = rdev->mc.mc_vram_size + rdev->mc.aper_size; + if (tmp > rdev->mc.aper_base) { + rdev->mc.vram_end = 0; } else { - tmp = rdev->mc.gtt_location + rdev->mc.gtt_size; - tmp += (rdev->mc.mc_vram_size - 1); - tmp &= ~(rdev->mc.mc_vram_size - 1); - if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) { - rdev->mc.vram_location = tmp; - } else { - printk(KERN_ERR "[drm] vram too big to fit " - "before or after GTT location.\n"); - return -EINVAL; - } + rdev->mc.vram_end = rdev->mc.aper_base - tmp; } + } + /* Some chips have an "issue" with the memory controller, the + * location must be aligned to the size. We just align it down, + * too bad if we walk over the top of system memory, we don't + * use DMA without a remapped anyway. + * Affected chips are rv280, all r3xx, and all r4xx, but not IGP + */ + rdev->mc.vram_start &= ~(rdev->mc.mc_vram_size - 1); + rdev->mc.vram_end = rdev->mc.vram_start + rdev->mc.mc_vram_size - 1; + + if ((0xFFFFFFFFUL - rdev->mc.vram_end - 1) > rdev->mc.gtt_size) { + rdev->mc.gtt_start = rdev->mc.vram_end + 1; } else { - rdev->mc.vram_location = 0; - tmp = rdev->mc.mc_vram_size; - tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); - rdev->mc.gtt_location = tmp; - } - rdev->mc.vram_start = rdev->mc.vram_location; - rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; - rdev->mc.gtt_start = rdev->mc.gtt_location; - rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; - DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20)); - DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n", - (unsigned)rdev->mc.vram_location, - (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1)); - DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20)); - DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n", - (unsigned)rdev->mc.gtt_location, - (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1)); + if (rdev->mc.vram_start < rdev->mc.gtt_size) { + /* net enought place before VRAM */ + dev_err(rdev->dev, "GTT too big to fit before or " + "after VRAM [0x%08X 0x%08X-0x%08X]\n", + (unsigned)rdev->mc.gtt_size, + (unsigned)rdev->mc.vram_start, + (unsigned)rdev->mc.vram_end); + return -EINVAL; + } + rdev->mc.gtt_start = rdev->mc.vram_start - rdev->mc.gtt_size; + } + rdev->mc.gtt_end = rdev->mc.gtt_start + rdev->mc.gtt_size - 1; + dev_info(rdev->dev, "VRAM: %dM 0x%08X - 0x%08X (%dM used)\n", + (unsigned)(rdev->mc.mc_vram_size >> 20), + (unsigned)rdev->mc.vram_start, + (unsigned)rdev->mc.vram_end, + (unsigned)(rdev->mc.vram_size >> 20)); + dev_info(rdev->dev, "GTT: %dM 0x%08X - 0x%08X\n", + (unsigned)(rdev->mc.gtt_size >> 20), + (unsigned)rdev->mc.gtt_start, + (unsigned)rdev->mc.gtt_end); return 0; } diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c index 66055b3..b78c897 100644 --- a/drivers/gpu/drm/radeon/radeon_fb.c +++ b/drivers/gpu/drm/radeon/radeon_fb.c @@ -257,7 +257,7 @@ int radeonfb_create(struct drm_device *dev, info->flags = FBINFO_DEFAULT; info->fbops = &radeonfb_ops; - tmp = fb_gpuaddr - rdev->mc.vram_location; + tmp = fb_gpuaddr - rdev->mc.vram_start; info->fix.smem_start = rdev->mc.aper_base + tmp; info->fix.smem_len = size; info->screen_base = fbptr; @@ -267,7 +267,7 @@ int radeonfb_create(struct drm_device *dev, /* setup aperture base/size for vesafb takeover */ info->aperture_base = rdev->ddev->mode_config.fb_base; - info->aperture_size = rdev->mc.real_vram_size; + info->aperture_size = rdev->mc.vram_size; info->fix.mmio_start = 0; info->fix.mmio_len = 0; @@ -335,7 +335,7 @@ int radeonfb_probe(struct drm_device *dev) int bpp_sel = 32; /* select 8 bpp console on RN50 or 16MB cards */ - if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32*1024*1024)) + if (ASIC_IS_RN50(rdev) || rdev->mc.vram_size <= (32*1024*1024)) bpp_sel = 8; return drm_fb_helper_single_fb_probe(dev, bpp_sel, &radeonfb_create); diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c index e927f99..1ef4361 100644 --- a/drivers/gpu/drm/radeon/radeon_gem.c +++ b/drivers/gpu/drm/radeon/radeon_gem.c @@ -156,8 +156,8 @@ int radeon_gem_info_ioctl(struct drm_device *dev, void *data, struct radeon_device *rdev = dev->dev_private; struct drm_radeon_gem_info *args = data; - args->vram_size = rdev->mc.real_vram_size; - args->vram_visible = rdev->mc.real_vram_size; + args->vram_size = rdev->mc.vram_size; + args->vram_visible = rdev->mc.vram_size; if (rdev->stollen_vga_memory) args->vram_visible -= radeon_bo_size(rdev->stollen_vga_memory); if (rdev->fbdev_rbo) diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c index b82ede9..4ee39b1 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c @@ -467,7 +467,7 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, /* if scanout was in GTT this really wouldn't work */ /* crtc offset is from display base addr not FB location */ - radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location; + radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start; base -= radeon_crtc->legacy_display_base_addr; diff --git a/drivers/gpu/drm/radeon/radeon_test.c b/drivers/gpu/drm/radeon/radeon_test.c index 391c973..94ac64c 100644 --- a/drivers/gpu/drm/radeon/radeon_test.c +++ b/drivers/gpu/drm/radeon/radeon_test.c @@ -186,7 +186,7 @@ void radeon_test_moves(struct radeon_device *rdev) radeon_bo_kunmap(gtt_obj[i]); DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n", - gtt_addr - rdev->mc.gtt_location); + gtt_addr - rdev->mc.gtt_start); } out_cleanup: diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index 4ca7dfc..fef517f 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c @@ -150,7 +150,7 @@ static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, man->default_caching = TTM_PL_FLAG_CACHED; break; case TTM_PL_TT: - man->gpu_offset = rdev->mc.gtt_location; + man->gpu_offset = rdev->mc.gtt_start; man->available_caching = TTM_PL_MASK_CACHING; man->default_caching = TTM_PL_FLAG_CACHED; man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; @@ -180,7 +180,7 @@ static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, break; case TTM_PL_VRAM: /* "On-card" video ram */ - man->gpu_offset = rdev->mc.vram_location; + man->gpu_offset = rdev->mc.vram_start; man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_NEEDS_IOREMAP | TTM_MEMTYPE_FLAG_MAPPABLE; @@ -246,10 +246,10 @@ static int radeon_move_blit(struct ttm_buffer_object *bo, switch (old_mem->mem_type) { case TTM_PL_VRAM: - old_start += rdev->mc.vram_location; + old_start += rdev->mc.vram_start; break; case TTM_PL_TT: - old_start += rdev->mc.gtt_location; + old_start += rdev->mc.gtt_start; break; default: DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); @@ -257,10 +257,10 @@ static int radeon_move_blit(struct ttm_buffer_object *bo, } switch (new_mem->mem_type) { case TTM_PL_VRAM: - new_start += rdev->mc.vram_location; + new_start += rdev->mc.vram_start; break; case TTM_PL_TT: - new_start += rdev->mc.gtt_location; + new_start += rdev->mc.gtt_start; break; default: DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); @@ -482,7 +482,7 @@ int radeon_ttm_init(struct radeon_device *rdev) return r; } r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, - rdev->mc.real_vram_size >> PAGE_SHIFT); + rdev->mc.vram_size >> PAGE_SHIFT); if (r) { DRM_ERROR("Failed initializing VRAM heap.\n"); return r; @@ -502,20 +502,15 @@ int radeon_ttm_init(struct radeon_device *rdev) radeon_bo_unref(&rdev->stollen_vga_memory); return r; } - DRM_INFO("radeon: %uM of VRAM memory ready\n", - (unsigned)rdev->mc.real_vram_size / (1024 * 1024)); r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, rdev->mc.gtt_size >> PAGE_SHIFT); if (r) { DRM_ERROR("Failed initializing GTT heap.\n"); return r; } - DRM_INFO("radeon: %uM of GTT memory ready.\n", - (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; } - r = radeon_ttm_debugfs_init(rdev); if (r) { DRM_ERROR("Failed to init debugfs\n"); diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c index eda6d75..c944bff 100644 --- a/drivers/gpu/drm/radeon/rs400.c +++ b/drivers/gpu/drm/radeon/rs400.c @@ -150,9 +150,8 @@ int rs400_gart_enable(struct radeon_device *rdev) WREG32(RADEON_AGP_BASE, 0xFFFFFFFF); WREG32(RS480_AGP_BASE_2, 0); } - tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; - tmp = REG_SET(RS690_MC_AGP_TOP, tmp >> 16); - tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_location >> 16); + tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); + tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp); tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; @@ -353,8 +352,8 @@ static int rs400_mc_init(struct radeon_device *rdev) /* Setup GPU memory space */ tmp = RREG32(R_00015C_NB_TOM); - rdev->mc.vram_location = G_00015C_MC_FB_START(tmp) << 16; - rdev->mc.gtt_location = 0xFFFFFFFFUL; + rdev->mc.vram_start = G_00015C_MC_FB_START(tmp) << 16; + rdev->mc.gtt_start = 0xFFFFFFFFUL; r = radeon_mc_setup(rdev); if (r) return r; diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c index fd5ab01..bbc5e2a 100644 --- a/drivers/gpu/drm/radeon/rs600.c +++ b/drivers/gpu/drm/radeon/rs600.c @@ -53,8 +53,8 @@ int rs600_mc_init(struct radeon_device *rdev) /* Setup GPU memory space */ tmp = RREG32_MC(R_000004_MC_FB_LOCATION); - rdev->mc.vram_location = G_000004_MC_FB_START(tmp) << 16; - rdev->mc.gtt_location = 0xffffffffUL; + rdev->mc.vram_start = G_000004_MC_FB_START(tmp) << 16; + rdev->mc.gtt_start = 0xffffffffUL; r = radeon_mc_setup(rdev); if (r) return r; @@ -468,17 +468,14 @@ void rs600_vram_info(struct radeon_device *rdev) rdev->mc.vram_is_ddr = true; rdev->mc.vram_width = 128; - rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); - rdev->mc.mc_vram_size = rdev->mc.real_vram_size; - + rdev->mc.mc_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); - - if (rdev->mc.mc_vram_size > rdev->mc.aper_size) - rdev->mc.mc_vram_size = rdev->mc.aper_size; - - if (rdev->mc.real_vram_size > rdev->mc.aper_size) - rdev->mc.real_vram_size = rdev->mc.aper_size; + rdev->mc.vram_size = rdev->mc.mc_vram_size; + if (rdev->mc.vram_size > rdev->mc.aper_size) + rdev->mc.vram_size = rdev->mc.aper_size; + if (radeon_vram_limit && radeon_vram_limit < rdev->mc.vram_size) + rdev->mc.vram_size = radeon_vram_limit; } void rs600_bandwidth_update(struct radeon_device *rdev) diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c index eb486ee..d994dc2 100644 --- a/drivers/gpu/drm/radeon/rs690.c +++ b/drivers/gpu/drm/radeon/rs690.c @@ -138,17 +138,14 @@ void rs690_vram_info(struct radeon_device *rdev) rdev->mc.vram_is_ddr = true; rdev->mc.vram_width = 128; - rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); - rdev->mc.mc_vram_size = rdev->mc.real_vram_size; - + rdev->mc.mc_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); - - if (rdev->mc.mc_vram_size > rdev->mc.aper_size) - rdev->mc.mc_vram_size = rdev->mc.aper_size; - - if (rdev->mc.real_vram_size > rdev->mc.aper_size) - rdev->mc.real_vram_size = rdev->mc.aper_size; + rdev->mc.vram_size = rdev->mc.mc_vram_size; + if (rdev->mc.vram_size > rdev->mc.aper_size) + rdev->mc.vram_size = rdev->mc.aper_size; + if (radeon_vram_limit && radeon_vram_limit < rdev->mc.vram_size) + rdev->mc.vram_size = radeon_vram_limit; rs690_pm_info(rdev); /* FIXME: we should enforce default clock in case GPU is not in @@ -169,8 +166,8 @@ static int rs690_mc_init(struct radeon_device *rdev) /* Setup GPU memory space */ tmp = RREG32_MC(R_000100_MCCFG_FB_LOCATION); - rdev->mc.vram_location = G_000100_MC_FB_START(tmp) << 16; - rdev->mc.gtt_location = 0xFFFFFFFFUL; + rdev->mc.vram_start = G_000100_MC_FB_START(tmp) << 16; + rdev->mc.gtt_start = 0xFFFFFFFFUL; r = radeon_mc_setup(rdev); if (r) return r; diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c index 7793239..2e9a38f 100644 --- a/drivers/gpu/drm/radeon/rv515.c +++ b/drivers/gpu/drm/radeon/rv515.c @@ -425,7 +425,7 @@ void rv515_mc_program(struct radeon_device *rdev) if (rv515_mc_wait_for_idle(rdev)) dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); /* Write VRAM size in case we are limiting it */ - WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); + WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.mc_vram_size); /* Program MC, should be a 32bits limited address space */ WREG32_MC(R_000001_MC_FB_LOCATION, S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index 78e200b..86a716a 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c @@ -813,49 +813,21 @@ int rv770_mc_init(struct radeon_device *rdev) rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); /* Setup GPU memory space */ rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); - rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); - - if (rdev->mc.mc_vram_size > rdev->mc.aper_size) - rdev->mc.mc_vram_size = rdev->mc.aper_size; - - if (rdev->mc.real_vram_size > rdev->mc.aper_size) - rdev->mc.real_vram_size = rdev->mc.aper_size; - + rdev->mc.vram_size = rdev->mc.mc_vram_size; + if (rdev->mc.vram_size > rdev->mc.aper_size) + rdev->mc.vram_size = rdev->mc.aper_size; + if (radeon_vram_limit && radeon_vram_limit < rdev->mc.vram_size) + rdev->mc.vram_size = radeon_vram_limit; + rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; if (rdev->flags & RADEON_IS_AGP) { + /* gtt_size is setup by radeon_agp_init */ r = radeon_agp_init(rdev); if (r) return r; - /* gtt_size is setup by radeon_agp_init */ - rdev->mc.gtt_location = rdev->mc.agp_base; - tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; - /* Try to put vram before or after AGP because we - * we want SYSTEM_APERTURE to cover both VRAM and - * AGP so that GPU can catch out of VRAM/AGP access - */ - if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) { - /* Enought place before */ - rdev->mc.vram_location = rdev->mc.gtt_location - - rdev->mc.mc_vram_size; - } else if (tmp > rdev->mc.mc_vram_size) { - /* Enought place after */ - rdev->mc.vram_location = rdev->mc.gtt_location + - rdev->mc.gtt_size; - } else { - /* Try to setup VRAM then AGP might not - * not work on some card - */ - rdev->mc.vram_location = 0x00000000UL; - rdev->mc.gtt_location = rdev->mc.mc_vram_size; - } - } else { - rdev->mc.vram_location = 0x00000000UL; - rdev->mc.gtt_location = rdev->mc.mc_vram_size; - rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; } - rdev->mc.vram_start = rdev->mc.vram_location; - rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; - rdev->mc.gtt_start = rdev->mc.gtt_location; - rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; + r = radeon_mc_setup(rdev); + if (r) + return r; /* FIXME: we should enforce default clock in case GPU is not in * default setup */ -- 1.6.5.2 ------------------------------------------------------------------------------ Return on Information: Google Enterprise Search pays you back Get the facts. http://p.sf.net/sfu/google-dev2dev -- _______________________________________________ Dri-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/dri-devel
