Luca Barbieri wrote: > While this is almost surely a good idea, note that userspace caching > and suballocation substantially improves Mesa performance even on PCIe > systems. > This is mostly due to the unavoidable overhead of kernel calls and > pagetable modifications,
> as well as the avoidable linear search the > kernel currently does to find an empty space in virtual address space, > ^^^ Luca, I've never seen this show up high on a profile (yet). Do you see that with Nouveau? I used to have an rb-tree implementation of drm_mm_xxx lying around, but I didn't use it because I didn't have a case where it showed up? > as well as the additional pagefaults. > > Userspace caching and suballocation mean that you just have to compute > a pointer, which you cannot beat with any kernel-space solution. This > is also the way glibc allocates normal memory with malloc(), for the > same reason. > ------------------------------------------------------------------------------ Download Intel® Parallel Studio Eval Try the new software tools for yourself. Speed compiling, find bugs proactively, and fine-tune applications for parallel performance. See why Intel Parallel Studio got high marks during beta. http://p.sf.net/sfu/intel-sw-dev -- _______________________________________________ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
