Hi Alex,

On Wed, 10 Mar 2010 19:09:08 -0500, Alex Deucher wrote:
> Thanks to Jean for helping me with the i2c stuff.  I've attached
> Jean's bit algo patch as my radeon patch depends on it.  I'm not sure
> how we want to get that one upstream (either via drm or i2c).

i2c tree probably. I think I can push it to Linus quickly, it's a small
one, can't cause a regression, and rc2 isn't out yet.

> Previously, the radeon drm registered i2c buses using the radeon algo
> which would use either the hw i2c engine or bit banging depending on
> the bus in question (some are hw capable, others are not, some chips
> don't have support for their hw engines yet, etc.).  The tricky part
> was that the radeon i2c bit buses require some gpio magic before and
> after a transaction which bit algo didn't previously support.
> Unfortunately, it exposed the internal bit algo bus as well we as the
> radeon algo bus which is bad.  With these patches, if the hw engine is
> supported, we use the radeon algo, if not, we use bit algo directly
> with the pre/post_xfer functions to fix up the gpios.

Looks good. I have one suggestion of possible improvement for the
future. You could turn rec->hw_capable into a function pointer,
pointing to the appropriate r*_hw_i2c_xfer() function. This would be
more efficient that looking up the right function each time
radeon_hw_i2c_xfer() is called. This would also avoid checking the chip
model at registration time, to decide between hardware and software
implementation, as these tests could easily go out of sync with what
is actually implemented, when you add support for newer chips.

> I've tested on several radeons, but more tested would be nice.

I have the following in my machine:
02:00.0 VGA compatible controller: ATI Technologies Inc RV280 [Radeon 9200] 
(rev 01)
02:00.1 Display controller: ATI Technologies Inc RV280 [Radeon 9200] 
(Secondary) (rev 01)

Can I help with testing? I can follow your instructions.

-- 
Jean Delvare

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