Looks like this one might have gotten lost in the shuffle. Alex
On Fri, Mar 5, 2010 at 2:55 PM, Alex Deucher <alexdeuc...@gmail.com> wrote: > From cec90cfdc0f20efcbcd266069a6a8234d230cc0b Mon Sep 17 00:00:00 2001 > From: Alex Deucher <alexdeuc...@gmail.com> > Date: Fri, 5 Mar 2010 14:50:37 -0500 > Subject: [PATCH] drm/radeon/kms: gfx init fixes for r6xx/r7xx > > This fixes some issues with the last gfx init patch. > > Signed-off-by: Alex Deucher <alexdeuc...@gmail.com> > --- > drivers/gpu/drm/radeon/r600.c | 1 + > drivers/gpu/drm/radeon/r600_cp.c | 3 +++ > drivers/gpu/drm/radeon/rv770.c | 3 +++ > 3 files changed, 7 insertions(+), 0 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c > index f9a8335..3980ec9 100644 > --- a/drivers/gpu/drm/radeon/r600.c > +++ b/drivers/gpu/drm/radeon/r600.c > @@ -1132,6 +1132,7 @@ void r600_gpu_init(struct radeon_device *rdev) > /* Setup pipes */ > WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); > WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); > + WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); > > tmp = R6XX_MAX_PIPES - > r600_count_pipe_bits((cc_gc_shader_pipe_config & > INACTIVE_QD_PIPES_MASK) >> 8); > WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); > diff --git a/drivers/gpu/drm/radeon/r600_cp.c > b/drivers/gpu/drm/radeon/r600_cp.c > index 40416c0..68e6f43 100644 > --- a/drivers/gpu/drm/radeon/r600_cp.c > +++ b/drivers/gpu/drm/radeon/r600_cp.c > @@ -1548,10 +1548,13 @@ static void r700_gfx_init(struct drm_device *dev, > > RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); > RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, > cc_gc_shader_pipe_config); > + RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, > cc_gc_shader_pipe_config); > > RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); > RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0); > RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0); > + RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0); > + RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0); > > num_qd_pipes = > R7XX_MAX_PIPES - > r600_count_pipe_bits((cc_gc_shader_pipe_config & > R600_INACTIVE_QD_PIPES_MASK) >> 8); > diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c > index 37887de..63c181b 100644 > --- a/drivers/gpu/drm/radeon/rv770.c > +++ b/drivers/gpu/drm/radeon/rv770.c > @@ -647,10 +647,13 @@ static void rv770_gpu_init(struct radeon_device *rdev) > > WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); > WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); > + WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); > WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); > > WREG32(CGTS_SYS_TCC_DISABLE, 0); > WREG32(CGTS_TCC_DISABLE, 0); > + WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); > + WREG32(CGTS_USER_TCC_DISABLE, 0); > > num_qd_pipes = > R7XX_MAX_PIPES - > r600_count_pipe_bits((cc_gc_shader_pipe_config & > INACTIVE_QD_PIPES_MASK) >> 8); > -- > 1.5.6.3 > ------------------------------------------------------------------------------ Download Intel® Parallel Studio Eval Try the new software tools for yourself. Speed compiling, find bugs proactively, and fine-tune applications for parallel performance. See why Intel Parallel Studio got high marks during beta. http://p.sf.net/sfu/intel-sw-dev -- _______________________________________________ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
