On Fri, 26 Mar 2010 11:07:18 -0700
Jesse Barnes <jbar...@virtuousgeek.org> wrote:
> Most of the PIPE*STAT status bits will continue to flip even if they're
> not generating interrupts. So only check for those that can cause
> interrupts when we reach the i915_irq_handler, since it might be shared
> and we don't want to process spurious events.
>
> Signed-off-by: Jesse Barnes <jbar...@virtuousgeek.org>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_irq.c | 6 ++++--
> 2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index aba8260..abf2713 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -260,6 +260,7 @@ typedef struct drm_i915_private {
> /** Cached value of IMR to avoid reads in updating the bitfield */
> u32 irq_mask_reg;
> u32 pipestat[2];
> + u32 pipe_mask[2];
> /** splitted irq regs for graphics and display engine on Ironlake,
> irq_mask_reg is still used for display irq. */
> u32 gt_irq_mask_reg;
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index eca0e5b..9519346 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -141,6 +141,7 @@ i915_enable_pipestat(drm_i915_private_t *dev_priv, int
> pipe, u32 mask)
> u32 reg = i915_pipestat(pipe);
>
> dev_priv->pipestat[pipe] |= mask;
> + dev_priv->pipe_mask[pipe] |= (mask >> 16);
> /* Enable the interrupt, clear any pending status */
> I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
> (void) I915_READ(reg);
> @@ -154,6 +155,7 @@ i915_disable_pipestat(drm_i915_private_t *dev_priv, int
> pipe, u32 mask)
> u32 reg = i915_pipestat(pipe);
>
> dev_priv->pipestat[pipe] &= ~mask;
> + dev_priv->pipe_mask[pipe] &= ~(mask >> 16);
> I915_WRITE(reg, dev_priv->pipestat[pipe]);
> (void) I915_READ(reg);
> }
> @@ -868,14 +870,14 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
> /*
> * Clear the PIPE(A|B)STAT regs before the IIR
> */
> - if (pipea_stats & 0x8000ffff) {
> + if (pipea_stats & dev_priv->pipe_mask[0]) {
> if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS)
> DRM_DEBUG_DRIVER("pipe a underrun\n");
> I915_WRITE(PIPEASTAT, pipea_stats);
> irq_received = 1;
> }
>
> - if (pipeb_stats & 0x8000ffff) {
> + if (pipeb_stats & dev_priv->pipe_mask[1]) {
> if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS)
> DRM_DEBUG_DRIVER("pipe b underrun\n");
> I915_WRITE(PIPEBSTAT, pipeb_stats);
Still testing 4-6 on GM45 to make sure I haven't broken anything on
non-gen3, additional testing would be appreciated too. These core
changes always make me nervous.
--
Jesse Barnes, Intel Open Source Technology Center
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--
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