Replace (1 << x) by BIT(x) as recommended by
checkpatch.pl
Signed-off-by: Anish Bhatt <an...@chelsio.com>
---
drivers/staging/wilc1000/wilc_wlan.c | 64 +++++++++++++++++-------------------
1 file changed, 31 insertions(+), 33 deletions(-)
diff --git a/drivers/staging/wilc1000/wilc_wlan.c
b/drivers/staging/wilc1000/wilc_wlan.c
index 7c53a2b..0202b37 100644
--- a/drivers/staging/wilc1000/wilc_wlan.c
+++ b/drivers/staging/wilc1000/wilc_wlan.c
@@ -306,9 +306,6 @@ typedef struct {
struct Ack_session_info *Free_head;
struct Ack_session_info *Alloc_head;
-#define TCP_FIN_MASK (1 << 0)
-#define TCP_SYN_MASK (1 << 1)
-#define TCP_Ack_MASK (1 << 4)
#define NOT_TCP_ACK (-1)
#define MAX_TCP_SESSION 25
@@ -709,7 +706,7 @@ INLINE void chip_allow_sleep(void)
/* Clear bit 1 */
g_wlan.hif_func.hif_read_reg(0xf0, ®);
- g_wlan.hif_func.hif_write_reg(0xf0, reg & ~(1 << 0));
+ g_wlan.hif_func.hif_write_reg(0xf0, reg & ~BIT(0));
}
INLINE void chip_wakeup(void)
@@ -721,10 +718,10 @@ INLINE void chip_wakeup(void)
do {
g_wlan.hif_func.hif_read_reg(1, ®);
/* Set bit 1 */
- g_wlan.hif_func.hif_write_reg(1, reg | (1 << 1));
+ g_wlan.hif_func.hif_write_reg(1, reg | BIT(1));
/* Clear bit 1*/
- g_wlan.hif_func.hif_write_reg(1, reg & ~(1 << 1));
+ g_wlan.hif_func.hif_write_reg(1, reg & ~BIT(1));
do {
/* Wait for the chip to stabilize*/
@@ -741,7 +738,7 @@ INLINE void chip_wakeup(void)
g_wlan.hif_func.hif_read_reg(0xf0, ®);
do {
/* Set bit 1 */
- g_wlan.hif_func.hif_write_reg(0xf0, reg | (1 << 0));
+ g_wlan.hif_func.hif_write_reg(0xf0, reg | BIT(0));
/* Check the clock status */
g_wlan.hif_func.hif_read_reg(0xf1, &clk_status_reg);
@@ -764,7 +761,8 @@ INLINE void chip_wakeup(void)
/* in case of failure, Reset the wakeup bit to
introduce a new edge on the next loop */
if ((clk_status_reg & 0x1) == 0) {
/* Reset bit 0 */
- g_wlan.hif_func.hif_write_reg(0xf0, reg & (~(1
<< 0)));
+ g_wlan.hif_func.hif_write_reg(0xf0, reg &
+ (~BIT(0)));
}
} while ((clk_status_reg & 0x1) == 0);
}
@@ -772,18 +770,18 @@ INLINE void chip_wakeup(void)
if (genuChipPSstate == CHIP_SLEEPING_MANUAL) {
g_wlan.hif_func.hif_read_reg(0x1C0C, ®);
- reg &= ~(1 << 0);
+ reg &= ~BIT(0);
g_wlan.hif_func.hif_write_reg(0x1C0C, reg);
if (wilc_get_chipid(false) >= 0x1002b0) {
/* Enable PALDO back right after wakeup */
uint32_t val32;
g_wlan.hif_func.hif_read_reg(0x1e1c, &val32);
- val32 |= (1 << 6);
+ val32 |= BIT(6);
g_wlan.hif_func.hif_write_reg(0x1e1c, val32);
g_wlan.hif_func.hif_read_reg(0x1e9c, &val32);
- val32 |= (1 << 6);
+ val32 |= BIT(6);
g_wlan.hif_func.hif_write_reg(0x1e9c, val32);
}
}
@@ -797,19 +795,19 @@ INLINE void chip_wakeup(void)
if ((g_wlan.io_func.io_type & 0x1) == HIF_SPI) {
g_wlan.hif_func.hif_read_reg(1, ®);
/* Make sure bit 1 is 0 before we start. */
- g_wlan.hif_func.hif_write_reg(1, reg & ~(1 << 1));
+ g_wlan.hif_func.hif_write_reg(1, reg & ~BIT(1));
/* Set bit 1 */
- g_wlan.hif_func.hif_write_reg(1, reg | (1 << 1));
+ g_wlan.hif_func.hif_write_reg(1, reg | BIT(1));
/* Clear bit 1*/
- g_wlan.hif_func.hif_write_reg(1, reg & ~(1 << 1));
+ g_wlan.hif_func.hif_write_reg(1, reg & ~BIT(1));
} else if ((g_wlan.io_func.io_type & 0x1) == HIF_SDIO) {
/* Make sure bit 0 is 0 before we start. */
g_wlan.hif_func.hif_read_reg(0xf0, ®);
- g_wlan.hif_func.hif_write_reg(0xf0, reg & ~(1 << 0));
+ g_wlan.hif_func.hif_write_reg(0xf0, reg & ~BIT(0));
/* Set bit 1 */
- g_wlan.hif_func.hif_write_reg(0xf0, reg | (1 << 0));
+ g_wlan.hif_func.hif_write_reg(0xf0, reg | BIT(0));
/* Clear bit 1 */
- g_wlan.hif_func.hif_write_reg(0xf0, reg & ~(1 << 0));
+ g_wlan.hif_func.hif_write_reg(0xf0, reg & ~BIT(0));
}
do {
@@ -827,18 +825,18 @@ INLINE void chip_wakeup(void)
if (genuChipPSstate == CHIP_SLEEPING_MANUAL) {
g_wlan.hif_func.hif_read_reg(0x1C0C, ®);
- reg &= ~(1 << 0);
+ reg &= ~BIT(0);
g_wlan.hif_func.hif_write_reg(0x1C0C, reg);
if (wilc_get_chipid(false) >= 0x1002b0) {
/* Enable PALDO back right after wakeup */
uint32_t val32;
g_wlan.hif_func.hif_read_reg(0x1e1c, &val32);
- val32 |= (1 << 6);
+ val32 |= BIT(6);
g_wlan.hif_func.hif_write_reg(0x1e1c, val32);
g_wlan.hif_func.hif_read_reg(0x1e9c, &val32);
- val32 |= (1 << 6);
+ val32 |= BIT(6);
g_wlan.hif_func.hif_write_reg(0x1e9c, val32);
}
}
@@ -939,7 +937,7 @@ static int wilc_wlan_handle_txq(uint32_t *pu32TxqCount)
PRINT_D(TX_DBG, "VMMTable entry size = %d\n",
vmm_table[i]);
if (tqe->type == WILC_CFG_PKT) {
- vmm_table[i] |= (1 << 10);
+ vmm_table[i] |= BIT(10);
PRINT_D(TX_DBG, "VMMTable entry changed
for CFG packet = %d\n", vmm_table[i]);
}
#ifdef BIG_ENDIAN
@@ -1108,9 +1106,9 @@ static int wilc_wlan_handle_txq(uint32_t *pu32TxqCount)
/*setting bit 30 in the host header to indicate
mgmt frame*/
#ifdef WILC_AP_EXTERNAL_MLME
if (tqe->type == WILC_MGMT_PKT)
- header |= (1 << 30);
+ header |= BIT(30);
else
- header &= ~(1 << 30);
+ header &= ~BIT(30);
#endif
#ifdef BIG_ENDIAN
@@ -1608,7 +1606,7 @@ static int wilc_wlan_start(void)
#else
if (p->io_func.io_type == HIF_SDIO) {
reg = 0;
- reg |= (1 << 3); /* bug 4456 and 4557 */
+ reg |= BIT(3); /* bug 4456 and 4557 */
} else if (p->io_func.io_type == HIF_SPI) {
reg = 1;
}
@@ -1727,7 +1725,7 @@ static int wilc_wlan_stop(void)
return ret;
}
- reg &= ~(1 << 10);
+ reg &= ~BIT(10);
ret = p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg);
@@ -1748,9 +1746,9 @@ static int wilc_wlan_stop(void)
}
PRINT_D(GENERIC_DBG, "Read RESET Reg %x : Retry%d\n", reg,
timeout);
/*Workaround to ensure that the chip is actually reset*/
- if ((reg & (1 << 10))) {
+ if ((reg & BIT(10))) {
PRINT_D(GENERIC_DBG, "Bit 10 not reset : Retry %d\n",
timeout);
- reg &= ~(1 << 10);
+ reg &= ~BIT(10);
ret = p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg);
timeout--;
} else {
@@ -1770,10 +1768,11 @@ static int wilc_wlan_stop(void)
/******************************************************************************/
/* This was add at Bug 4595 to reset the chip while maintaining the bus state
*/
/******************************************************************************/
- reg = ((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 8) | (1 << 9)
| (1 << 26) | (1 << 29) | (1 << 30) | (1 << 31)); /**/
+ reg = (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(8) | BIT(9) |
+ BIT(26) | BIT(29) | BIT(30) | BIT(31)); /**/
/**/
p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg);
/**/
- reg = ~(1 << 10);
/**/
+ reg = ~BIT(10);
/**/
ret = p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg);
/**/
/******************************************************************************/
@@ -2017,7 +2016,7 @@ uint32_t init_chip(void)
wilc_debug(N_ERR, "[wilc start]: fail read reg 0x1118
...\n");
return ret;
}
- reg |= (1 << 0);
+ reg |= BIT(0);
ret = g_wlan.hif_func.hif_write_reg(0x1118, reg);
if (!ret) {
wilc_debug(N_ERR, "[wilc start]: fail write reg 0x1118
...\n");
@@ -2283,7 +2282,6 @@ _fail_:
}
-#define BIT31 (1 << 31)
u16 Set_machw_change_vir_if(bool bValue)
{
u16 ret;
@@ -2297,9 +2295,9 @@ u16 Set_machw_change_vir_if(bool bValue)
}
if (bValue)
- reg |= (BIT31);
+ reg |= BIT(31);
else
- reg &= ~(BIT31);
+ reg &= ~BIT(31);
ret = (&g_wlan)->hif_func.hif_write_reg(WILC_CHANGING_VIR_IF, reg);
--
2.5.1
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