Factor out a new function 'mt7621_enable_phy' for enabling the
pcie phy for each port and call it from 'mt7621_pcie_enable_port'.
Signed-off-by: Sergio Paracuellos <sergio.paracuel...@gmail.com>
---
drivers/staging/mt7621-pci/pci-mt7621.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 0d4b222..f9fec9a 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -388,6 +388,14 @@ set_phy_for_ssc(struct mt7621_pcie_port *port)
pcie_write(pcie, val, offset);
}
+static void mt7621_enable_phy(struct mt7621_pcie_port *port)
+{
+ /* MT7621 E2 */
+ if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101)
+ bypass_pipe_rst(port);
+ set_phy_for_ssc(port);
+}
+
static void setup_cm_memory_region(struct resource *mem_resource)
{
resource_size_t mask;
@@ -582,6 +590,8 @@ static void mt7621_pcie_enable_port(struct mt7621_pcie_port
*port)
val |= BIT(20 + slot);
pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
}
+
+ mt7621_enable_phy(port);
}
static int mt7621_pcie_request_resources(struct mt7621_pcie *pcie,
@@ -664,9 +674,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
u32 slot = port->slot;
mt7621_pcie_enable_port(port);
- if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621
E2
- bypass_pipe_rst(port);
- set_phy_for_ssc(port);
val = read_config(pcie, slot, 0x70c);
dev_info(dev, "Port %d N_FTS = %x\n", (unsigned int)val, slot);
}
--
2.7.4
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