Branch: refs/heads/thaines/x86_registers
Home: https://github.com/dyninst/dyninst
Commit: bea00457ccd7b0f68cab5df89edade5822c306de
https://github.com/dyninst/dyninst/commit/bea00457ccd7b0f68cab5df89edade5822c306de
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2023-11-16 (Thu, 16 Nov 2023)
Changed paths:
M common/h/registers/x86_regs.h
Log Message:
-----------
Improve comments for register lengths
Commit: 3f605a7b04e210dbae793cbd6d82f3efab99b836
https://github.com/dyninst/dyninst/commit/3f605a7b04e210dbae793cbd6d82f3efab99b836
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2023-11-16 (Thu, 16 Nov 2023)
Changed paths:
M common/h/registers/x86_regs.h
M common/src/registers/MachRegister.C
Log Message:
-----------
Separate MMX/3DNow! and x87 register lengths
The MMX* registers are only the lower 64 bits of the st* ones.
Commit: 68b6746fa99fb8cb87fea79504a17f3af98b49f8
https://github.com/dyninst/dyninst/commit/68b6746fa99fb8cb87fea79504a17f3af98b49f8
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2023-11-16 (Thu, 16 Nov 2023)
Changed paths:
M common/h/registers/x86_regs.h
M common/src/registers/MachRegister.C
Log Message:
-----------
Separate MMX/3DNow! and x87 register categories
Commit: c09beecb90e74787f92c92ed602fd797ba6b42d6
https://github.com/dyninst/dyninst/commit/c09beecb90e74787f92c92ed602fd797ba6b42d6
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2023-11-16 (Thu, 16 Nov 2023)
Changed paths:
M common/h/registers/x86_regs.h
Log Message:
-----------
Reorder the length flags
This puts them in more of a chronological order.
Commit: 22ff95739bb1194425f58953ef4418adb6f90fd9
https://github.com/dyninst/dyninst/commit/22ff95739bb1194425f58953ef4418adb6f90fd9
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2023-11-17 (Fri, 17 Nov 2023)
Changed paths:
M common/h/registers/x86_regs.h
Log Message:
-----------
Improve comments for register categories
Commit: c1caea107e1464067eaf0027a5cf78f39e97a33e
https://github.com/dyninst/dyninst/commit/c1caea107e1464067eaf0027a5cf78f39e97a33e
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2023-11-17 (Fri, 17 Nov 2023)
Changed paths:
M common/h/registers/x86_regs.h
Log Message:
-----------
Reorder register categories
This puts them in more of a chronological order.
Commit: da18d1ceab931ecd5f6f51dce66e6b8b5d64a748
https://github.com/dyninst/dyninst/commit/da18d1ceab931ecd5f6f51dce66e6b8b5d64a748
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2023-11-17 (Fri, 17 Nov 2023)
Changed paths:
M common/h/registers/x86_regs.h
Log Message:
-----------
Add comments for aliased GPRs
No real comments here. Just added a separator.
Commit: a1168d5e11082dd555a4e13945a704197d92d45d
https://github.com/dyninst/dyninst/commit/a1168d5e11082dd555a4e13945a704197d92d45d
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2023-11-17 (Fri, 17 Nov 2023)
Changed paths:
M common/h/registers/x86_regs.h
Log Message:
-----------
Improve comments for EFLAGS fields
Commit: 367544ebe5607b07020000b119d47187544db50c
https://github.com/dyninst/dyninst/commit/367544ebe5607b07020000b119d47187544db50c
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2023-11-17 (Fri, 17 Nov 2023)
Changed paths:
M common/src/registers/MachRegister.C
Log Message:
-----------
Add conversion to ROSE register for FLAGC
FLAGC is the lower bit of the I/O Permission Level field in EFIELD.
Commit: 70c3a9aafb00ee6f9c36b0126a81c67b57d8c572
https://github.com/dyninst/dyninst/commit/70c3a9aafb00ee6f9c36b0126a81c67b57d8c572
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2023-11-17 (Fri, 17 Nov 2023)
Changed paths:
M common/src/registers/MachRegister.C
Log Message:
-----------
Add conversion to ROSE register for FLAGD
FLAGC is the upper bit of the I/O Permission Level field in EFIELD.
Commit: 7fb6af027a37ab433cb4596194b210025bec6848
https://github.com/dyninst/dyninst/commit/7fb6af027a37ab433cb4596194b210025bec6848
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2023-11-17 (Fri, 17 Nov 2023)
Changed paths:
M common/src/registers/MachRegister.C
Log Message:
-----------
Add conversion to ROSE register for Nested Task flag
Commit: daa925807f9512b986308a4a612474aa9f3bd192
https://github.com/dyninst/dyninst/commit/daa925807f9512b986308a4a612474aa9f3bd192
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2023-11-17 (Fri, 17 Nov 2023)
Changed paths:
M common/src/registers/MachRegister.C
Log Message:
-----------
Add conversion to ROSE register for Resume Flag
Commit: dadbe3d03e36fb6d448bff57c657695e37d6fe8b
https://github.com/dyninst/dyninst/commit/dadbe3d03e36fb6d448bff57c657695e37d6fe8b
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2023-11-17 (Fri, 17 Nov 2023)
Changed paths:
M common/h/registers/x86_regs.h
M common/src/registers/MachRegister.C
Log Message:
-----------
Add missing Virtual-8086 mode (VM) EFLAGS field
Commit: 8633f88e9b342f549936e2b4b49df8558b19ff15
https://github.com/dyninst/dyninst/commit/8633f88e9b342f549936e2b4b49df8558b19ff15
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2023-11-17 (Fri, 17 Nov 2023)
Changed paths:
M common/h/registers/x86_regs.h
M common/src/registers/MachRegister.C
Log Message:
-----------
Add missing Alignment Check/Access Control (AC) EFLAGS field
Commit: 0f1a845213e4651849bdd8bb9b4ea1dc002c28de
https://github.com/dyninst/dyninst/commit/0f1a845213e4651849bdd8bb9b4ea1dc002c28de
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2023-11-17 (Fri, 17 Nov 2023)
Changed paths:
M common/h/registers/x86_regs.h
M common/src/registers/MachRegister.C
Log Message:
-----------
Add missing Virtual Interrupt Flag (VIF) EFLAGS field
Commit: 5e120c59d7931dcc0fb07398252e8589e175b5f1
https://github.com/dyninst/dyninst/commit/5e120c59d7931dcc0fb07398252e8589e175b5f1
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2023-11-17 (Fri, 17 Nov 2023)
Changed paths:
M common/h/registers/x86_regs.h
M common/src/registers/MachRegister.C
Log Message:
-----------
Add missing Virtual Interrupt Pending (VIP) EFLAGS field
Commit: 31d36f2a724c38f20a035f4e99e68bc235d28be6
https://github.com/dyninst/dyninst/commit/31d36f2a724c38f20a035f4e99e68bc235d28be6
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2023-11-17 (Fri, 17 Nov 2023)
Changed paths:
M common/h/registers/x86_regs.h
M common/src/registers/MachRegister.C
Log Message:
-----------
Add missing ID Flag (ID) EFLAGS field
Commit: 3dde18f14d327722774d74eeb0620e00ae0b14ab
https://github.com/dyninst/dyninst/commit/3dde18f14d327722774d74eeb0620e00ae0b14ab
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2023-11-17 (Fri, 17 Nov 2023)
Changed paths:
M common/h/registers/x86_regs.h
Log Message:
-----------
Add comment for reserved bits in EFLAGS register.
Commit: 2a11b132877732d274bc62cf577a6bcc5bfdf568
https://github.com/dyninst/dyninst/commit/2a11b132877732d274bc62cf577a6bcc5bfdf568
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2023-11-17 (Fri, 17 Nov 2023)
Changed paths:
M common/h/registers/x86_regs.h
Log Message:
-----------
Move format comment closer to declaration of registers
It makes the information easier to find.
Commit: 00e56a19c0c3b75eaf1697cb69fc2ccf2814e5ef
https://github.com/dyninst/dyninst/commit/00e56a19c0c3b75eaf1697cb69fc2ccf2814e5ef
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2023-11-17 (Fri, 17 Nov 2023)
Changed paths:
M common/h/registers/x86_regs.h
M dataflowAPI/src/RegisterMap.C
Log Message:
-----------
Remove registers xmm8-xmm31 and aliases
These registers are only available in 64-bit mode.
From Intel(r) 64 and IA-32 Architectures Software Developer’s Manual
June 2021:
11.2.1 SSE2 in 64-Bit Mode and Compatibility Mode
In compatibility mode, SSE2 extensions function like they do in
protected mode. In 64-bit mode, eight additional XMM registers are
accessible. Registers XMM8-XMM15 are accessed by using REX prefixes.
14.1.1 256-Bit Wide SIMD Register Support
Intel AVX introduces support for 256-bit wide SIMD registers
(YMM0-YMM7 in operating modes that are 32-bit or less, YMM0-YMM15 in
64-bit mode).
15.1.2 32 SIMD Register Support
Intel AVX-512 instructions also support 32 SIMD registers in 64-bit
mode (XMM0-XMM31, YMM0-YMM31 and ZMM0-ZMM31). The number of available
vector registers in 32-bit mode is still 8.
Commit: 5127b10a510439f8e20cdac59c1499558bb5a18a
https://github.com/dyninst/dyninst/commit/5127b10a510439f8e20cdac59c1499558bb5a18a
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2023-11-17 (Fri, 17 Nov 2023)
Changed paths:
M common/h/registers/x86_regs.h
M common/src/registers/MachRegister.C
Log Message:
-----------
Fix avx-512 opmask size.
It's 64 bits, not 128.
From Intel(R) 64 and IA-32 Architectures Software Developer’s Manual
June 2021
15.6.1 OPMASK Register to Predicate Vector Data Processing
The opmask is a set of eight architectural registers of size
MAX_KL (64-bit).
Commit: d6c8a1cb199ea6f16417ff6b817e70856aec9e08
https://github.com/dyninst/dyninst/commit/d6c8a1cb199ea6f16417ff6b817e70856aec9e08
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2023-11-17 (Fri, 17 Nov 2023)
Changed paths:
M common/h/registers/x86_regs.h
M common/src/registers/MachRegister.C
Log Message:
-----------
Rename OCT to XMMS
This makes it consistent with the names used for the other vector
extensions.
Commit: 9d7f49f1415b7d1f5872613fe43c87f3370c5bac
https://github.com/dyninst/dyninst/commit/9d7f49f1415b7d1f5872613fe43c87f3370c5bac
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2023-11-17 (Fri, 17 Nov 2023)
Changed paths:
M common/h/registers/x86_regs.h
Log Message:
-----------
Reorganize register declarations for readability
Commit: 09587d056b42a0f4408cbfb8520e7f46b9a1c597
https://github.com/dyninst/dyninst/commit/09587d056b42a0f4408cbfb8520e7f46b9a1c597
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2023-11-17 (Fri, 17 Nov 2023)
Changed paths:
M common/h/registers/x86_regs.h
Log Message:
-----------
Improve descriptions in comment about format of constants
Compare:
https://github.com/dyninst/dyninst/compare/bea00457ccd7%5E...09587d056b42
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