Branch: refs/heads/master
Home: https://github.com/dyninst/dyninst
Commit: dfc3a849301e5a4d9a2f24be56031f4c2314a793
https://github.com/dyninst/dyninst/commit/dfc3a849301e5a4d9a2f24be56031f4c2314a793
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2023-11-28 (Tue, 28 Nov 2023)
Changed paths:
M common/h/registers/x86_64_regs.h
M common/h/registers/x86_regs.h
M common/src/registers/MachRegister.C
Log Message:
-----------
Add x86_{i386,64} memory-management and x87 control/status registers (#1636)
* Add the memory-management registers
The processor provides four memory-management registers (GDTR, LDTR,
IDTR, and TR) that specify the locations of the data structures which
control segmented memory management. See Section 2.4 in Volume 3 of
the Intel 64 and IA-32 Architectures Software Developer’s Manual from
June 2021 for details.
* Add mxcsr
This is the SSE Control Status Word register. The AMD64
ABI doc says it's 128 bits, but it's actually 32.
* Add x87/SSE/AVX control and status word registers
Without these, getBaseRegister will convert fcw, fsw, and mxcsr to a
register with category '<id> | W_REG | ST | Arch_x86_64' which is
incorrect. getBaseRegister should return the register unmodified.
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