Branch: refs/heads/thaines/roseregs_fix_aarch64
Home: https://github.com/dyninst/dyninst
Commit: 0435b9461cbefe967806d39b9076e93f35fcf8f5
https://github.com/dyninst/dyninst/commit/0435b9461cbefe967806d39b9076e93f35fcf8f5
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M dataflowAPI/rose/registers/aarch64.h
M dataflowAPI/rose/registers/convert.C
Log Message:
-----------
aarch64: fix PC conversion
This handles both the 32-bit and 64-bit SP representations.
Commit: c2eaa52db52d6e1413a29b6af1a6dcaa9050d836
https://github.com/dyninst/dyninst/commit/c2eaa52db52d6e1413a29b6af1a6dcaa9050d836
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M dataflowAPI/rose/registers/aarch64.h
M dataflowAPI/rose/registers/convert.C
Log Message:
-----------
aarch64: update conversion of zero register
This makes it more uniform and removes the hacky bit-twiddling of the
MachRegister by name.
Commit: 7489ba7decac89bddbfec1cb086c61ef56a109f4
https://github.com/dyninst/dyninst/commit/7489ba7decac89bddbfec1cb086c61ef56a109f4
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M dataflowAPI/rose/registers/aarch64.h
M dataflowAPI/rose/registers/convert.C
Log Message:
-----------
aarch64: update conversion of stack pointer
This makes it more uniform and removes the hacky bit-twiddling of the
MachRegister by name.
Commit: 0c9eeb0a47df46862f3327019e4d0a781a1b83f5
https://github.com/dyninst/dyninst/commit/0c9eeb0a47df46862f3327019e4d0a781a1b83f5
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M dataflowAPI/rose/registers/aarch64.h
M dataflowAPI/rose/registers/convert.C
Log Message:
-----------
aarch64: update conversion of pstate register
This makes it more uniform and removes the hacky bit-twiddling of the
MachRegister by name.
Commit: c55cd460360e0d50a71542ec4612773ed8b05a6c
https://github.com/dyninst/dyninst/commit/c55cd460360e0d50a71542ec4612773ed8b05a6c
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M dataflowAPI/rose/registers/aarch64.h
Log Message:
-----------
aarch64: update conversion of GPRs
The register IDs are not guaranteed to be sequential, so it's not
possible to do arithmetic on them.
Commit: a0f6524d010b5f2962751f24e86211f7e852b301
https://github.com/dyninst/dyninst/commit/a0f6524d010b5f2962751f24e86211f7e852b301
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M dataflowAPI/rose/registers/aarch64.h
Log Message:
-----------
aarch64: update conversion of FPRs
The register IDs are not guaranteed to be sequential, so it's not
possible to do arithmetic on them.
Commit: 0750803242e3641280bb04366b1e56bab3dc5e84
https://github.com/dyninst/dyninst/commit/0750803242e3641280bb04366b1e56bab3dc5e84
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2024-12-18 (Wed, 18 Dec 2024)
Changed paths:
M dataflowAPI/rose/registers/aarch64.h
Log Message:
-----------
aarch64: update conversion of pstate flags
This makes it uniform with the other conversions. Note: the complete
pstate register is treated separately from its individual fields in
ROSE.
Compare:
https://github.com/dyninst/dyninst/compare/0435b9461cbe%5E...0750803242e3
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