Branch: refs/heads/thaines/roseregs_fix_aarch64
Home: https://github.com/dyninst/dyninst
Commit: ea6ed8ff819a7401a21e625684cd228084625736
https://github.com/dyninst/dyninst/commit/ea6ed8ff819a7401a21e625684cd228084625736
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M dataflowAPI/rose/registers/aarch64.h
M dataflowAPI/rose/registers/convert.C
Log Message:
-----------
Fix PC conversion
This handles both the 32-bit and 64-bit SP representations.
Commit: f2e01108ceb96e508a7cddf39a6df7e925a26e39
https://github.com/dyninst/dyninst/commit/f2e01108ceb96e508a7cddf39a6df7e925a26e39
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M dataflowAPI/rose/registers/aarch64.h
M dataflowAPI/rose/registers/convert.C
Log Message:
-----------
Update conversion of zero register
This makes it more uniform and removes the hacky bit-twiddling of the
MachRegister by name.
Commit: cf3d07144420a4e1352de933dc98d35a36bc713f
https://github.com/dyninst/dyninst/commit/cf3d07144420a4e1352de933dc98d35a36bc713f
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M dataflowAPI/rose/registers/aarch64.h
M dataflowAPI/rose/registers/convert.C
Log Message:
-----------
Update conversion of stack pointer
This makes it more uniform and removes the hacky bit-twiddling of the
MachRegister by name.
Commit: ae4c89670e1d67dada975dd83d9e0662d54d2411
https://github.com/dyninst/dyninst/commit/ae4c89670e1d67dada975dd83d9e0662d54d2411
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M dataflowAPI/rose/registers/aarch64.h
M dataflowAPI/rose/registers/convert.C
Log Message:
-----------
Update conversion of pstate register
This makes it more uniform and removes the hacky bit-twiddling of the
MachRegister by name.
Commit: c088a84fd5828486dbcfd9eb2ca3d77d1e0aae38
https://github.com/dyninst/dyninst/commit/c088a84fd5828486dbcfd9eb2ca3d77d1e0aae38
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M dataflowAPI/rose/registers/aarch64.h
Log Message:
-----------
Update conversion of GPRs
The register IDs are not guaranteed to be sequential, so it's not
possible to do arithmetic on them.
Commit: 9e9a0426b3f8972771cad06f066df806efa4a86e
https://github.com/dyninst/dyninst/commit/9e9a0426b3f8972771cad06f066df806efa4a86e
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M dataflowAPI/rose/registers/aarch64.h
Log Message:
-----------
Update conversion of FPRs
The register IDs are not guaranteed to be sequential, so it's not
possible to do arithmetic on them.
Commit: 0d6ac541064e97fd269dab785506f0e80f8e1afb
https://github.com/dyninst/dyninst/commit/0d6ac541064e97fd269dab785506f0e80f8e1afb
Author: Tim Haines <thaines.as...@gmail.com>
Date: 2024-12-19 (Thu, 19 Dec 2024)
Changed paths:
M dataflowAPI/rose/registers/aarch64.h
Log Message:
-----------
Update conversion of pstate flags
This makes it uniform with the other conversions. Note: the complete
pstate register is treated separately from its individual fields in
ROSE.
Compare: https://github.com/dyninst/dyninst/compare/0750803242e3...0d6ac541064e
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