Branch: refs/heads/thaines/AbsRegionConverter_convert Home: https://github.com/dyninst/dyninst Commit: 808f3dd21e5351d489007f7952466cb2dd6c4469 https://github.com/dyninst/dyninst/commit/808f3dd21e5351d489007f7952466cb2dd6c4469 Author: Tim Haines <thaines.as...@gmail.com> Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths: M dataflowAPI/src/AbslocInterface.C Log Message: ----------- Preserve full register in AbsRegionConverter::convert(RegisterAST::Ptr) ROSE distinguishes partial registers from full ones, so that needs to be reflected here since this class is the main point of conversion between Dyninst and ROSE. Example from aarch64: 0x94C: ldr W0, [X1, W0, lsl 0x2] The created Assignment is @94c<[aarch64::x0]>[aarch64::x1]>[aarch64::x0]>H[] Note that the assignment thinks the first register is x0, rather than w0. Passing this through AssignmentConverter::convert, the generated ROSE expressions are SgAsmIntegerType:SgAsmDirectRegisterExpression for 0x94C W0 SgAsmIntegerType:SgAsmDirectRegisterExpression for 0x94C X1 SgAsmIntegerType:SgAsmDirectRegisterExpression for 0x94C W0 Now, the first operand is correct. However, this operand is not recognized in RegisterStateAST::writeRegister( const RegisterDescriptor&, const BaseSemantics::SValuePtr&, Dyninst::DataflowAPI::Result_t&, std::map<Dyninst::Absloc, Dyninst::Assignment::Ptr>& ) because the map was created using the data from the Assignment. This causes the instruction expansion in SymbolicExpansion::expandAarch64 to fail. The other option would be to check for base register equality in Absloc::operator==, but that would change the semantics of equivalent abstract locations. To unsubscribe from these emails, change your notification settings at https://github.com/dyninst/dyninst/settings/notifications _______________________________________________ Dyninst-api mailing list Dyninst-api@cs.wisc.edu https://lists.cs.wisc.edu/mailman/listinfo/dyninst-api