Branch: refs/heads/angushe/riscv-codegen
Home: https://github.com/dyninst/dyninst
Commit: 92d70523f97bb8b7ceadf625798f7a1f4d2cee48
https://github.com/dyninst/dyninst/commit/92d70523f97bb8b7ceadf625798f7a1f4d2cee48
Author: wxrdnx <wxr...@protonmail.com>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/sail/sail_to_rose.pl
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
64 ->XLENBITS
Commit: d6f50b80917d07319f4e595a21de13318d230c0d
https://github.com/dyninst/dyninst/commit/d6f50b80917d07319f4e595a21de13318d230c0d
Author: wxrdnx <wxr...@protonmail.com>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Rewrite constant constraints
Commit: c8af2bf83c34476b51a55df71c190d62061bd446
https://github.com/dyninst/dyninst/commit/c8af2bf83c34476b51a55df71c190d62061bd446
Author: wxrdnx <wxr...@protonmail.com>
Date: 2025-05-23 (Fri, 23 May 2025)
Changed paths:
M dyninstAPI/src/BPatch_memoryAccessAdapter.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Implement missing memory codegen and fix wrong emitImm
Compare: https://github.com/dyninst/dyninst/compare/cb922496c641...c8af2bf83c34
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