Branch: refs/heads/angushe/instruction-api-riscv
Home: https://github.com/dyninst/dyninst
Commit: 32f2a089827a8fde229d216778ef492c25e0add8
https://github.com/dyninst/dyninst/commit/32f2a089827a8fde229d216778ef492c25e0add8
Author: wxrdnx <[email protected]>
Date: 2025-12-04 (Thu, 04 Dec 2025)
Changed paths:
M instructionAPI/h/Instruction.h
M instructionAPI/src/Instruction.C
Log Message:
-----------
Add method getExplicitEncodedOperands
Commit: bc5df1bcb7bd9a9b226bb6ed85a2deac9ac1f5a8
https://github.com/dyninst/dyninst/commit/bc5df1bcb7bd9a9b226bb6ed85a2deac9ac1f5a8
Author: wxrdnx <[email protected]>
Date: 2025-12-04 (Thu, 04 Dec 2025)
Changed paths:
M instructionAPI/src/Instruction.C
Log Message:
-----------
Put m_size to its own line
Commit: 6b3da7be578cf71cab51635b4398e5687aa05f09
https://github.com/dyninst/dyninst/commit/6b3da7be578cf71cab51635b4398e5687aa05f09
Author: wxrdnx <[email protected]>
Date: 2025-12-04 (Thu, 04 Dec 2025)
Changed paths:
M common/src/arch-riscv64.h
Log Message:
-----------
Add comments for RISC-V general purpose registers values
Compare: https://github.com/dyninst/dyninst/compare/3966d7db5c75...6b3da7be578c
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