Branch: refs/heads/thaines/update_riscv_capstone
Home: https://github.com/dyninst/dyninst
Commit: 3e4a0687ed842198a87e93037065ed3c2d69ba2d
https://github.com/dyninst/dyninst/commit/3e4a0687ed842198a87e93037065ed3c2d69ba2d
Author: Tim Haines <[email protected]>
Date: 2026-02-06 (Fri, 06 Feb 2026)
Changed paths:
M instructionAPI/src/decoder/riscv/categories.h
Log Message:
-----------
RISCV_GRP_ISRV64 -> RISCV_FEATURE_ISRV64
Commit: 84369ed9c7091830cc99118469d5238f731427b3
https://github.com/dyninst/dyninst/commit/84369ed9c7091830cc99118469d5238f731427b3
Author: Tim Haines <[email protected]>
Date: 2026-02-06 (Fri, 06 Feb 2026)
Changed paths:
M instructionAPI/src/decoder/riscv/categories.h
Log Message:
-----------
RISCV_GRP_ISRV32 -> RISCV_FEATURE_ISRV32
Commit: df13d68bc69d1baaf29b091cb2077d89a1fda901
https://github.com/dyninst/dyninst/commit/df13d68bc69d1baaf29b091cb2077d89a1fda901
Author: Tim Haines <[email protected]>
Date: 2026-02-06 (Fri, 06 Feb 2026)
Changed paths:
M instructionAPI/src/decoder/riscv/categories.h
Log Message:
-----------
RISCV_REG_ZERO -> RISCV_REG_X0
Commit: 41e21d9273c2b6d4ee5ae1a30d96456478707bcb
https://github.com/dyninst/dyninst/commit/41e21d9273c2b6d4ee5ae1a30d96456478707bcb
Author: Tim Haines <[email protected]>
Date: 2026-02-06 (Fri, 06 Feb 2026)
Changed paths:
M instructionAPI/src/decoder/riscv/categories.h
Log Message:
-----------
RISCV_REG_RA -> RISCV_REG_X1
Commit: d125406deef25912be9024db332a70a6424a5e81
https://github.com/dyninst/dyninst/commit/d125406deef25912be9024db332a70a6424a5e81
Author: Tim Haines <[email protected]>
Date: 2026-02-06 (Fri, 06 Feb 2026)
Changed paths:
M instructionAPI/src/decoder/riscv/register_xlat.C
Log Message:
-----------
RISCV_REG_F<N>_32 -> RISCV_REG_F<N>_F
Commit: 91072cb80151dfab145050630f73601aa068cf4c
https://github.com/dyninst/dyninst/commit/91072cb80151dfab145050630f73601aa068cf4c
Author: Tim Haines <[email protected]>
Date: 2026-02-06 (Fri, 06 Feb 2026)
Changed paths:
M instructionAPI/src/decoder/riscv/register_xlat.C
Log Message:
-----------
RISCV_REG_F<N>_64 -> RISCV_REG_F<N>_D
Commit: 265f4e010af70ed7bfb568b6b422ebb75f3b3f91
https://github.com/dyninst/dyninst/commit/265f4e010af70ed7bfb568b6b422ebb75f3b3f91
Author: Tim Haines <[email protected]>
Date: 2026-02-06 (Fri, 06 Feb 2026)
Changed paths:
M instructionAPI/src/decoder/riscv/opcode_xlat.C
Log Message:
-----------
RISCV_INS_AMOADD_X_AQ_RL -> RISCV_INS_AMOADD_X_AQRL
Commit: 0f61ab0d09d9c2ae7cad1e75082861f0077132bc
https://github.com/dyninst/dyninst/commit/0f61ab0d09d9c2ae7cad1e75082861f0077132bc
Author: Tim Haines <[email protected]>
Date: 2026-02-06 (Fri, 06 Feb 2026)
Changed paths:
M common/h/mnemonics/riscv64_entryIDs.h
M instructionAPI/src/decoder/riscv/opcode_xlat.C
Log Message:
-----------
Remove uret instruction
It seems like Capstone no longer supports it.
Commit: dbb8df3d8953e5209a6d67a090eb04d4113ab073
https://github.com/dyninst/dyninst/commit/dbb8df3d8953e5209a6d67a090eb04d4113ab073
Author: Tim Haines <[email protected]>
Date: 2026-02-06 (Fri, 06 Feb 2026)
Changed paths:
M instructionAPI/src/decoder/riscv/decoder.C
Log Message:
-----------
RISCV_REG_ZERO -> RISCV_REG_X0 -- REBASE
Commit: 731ce5c8a0a5293608a5b1c0c1c36984dbe89f40
https://github.com/dyninst/dyninst/commit/731ce5c8a0a5293608a5b1c0c1c36984dbe89f40
Author: Tim Haines <[email protected]>
Date: 2026-02-06 (Fri, 06 Feb 2026)
Changed paths:
M instructionAPI/src/decoder/riscv/decoder.C
Log Message:
-----------
RISCV_REG_RA -> RISCV_REG_X1 -- REBASE
Commit: a0b4ea8abcfde5ba26068c78fb349f32e7bdde1b
https://github.com/dyninst/dyninst/commit/a0b4ea8abcfde5ba26068c78fb349f32e7bdde1b
Author: Tim Haines <[email protected]>
Date: 2026-02-06 (Fri, 06 Feb 2026)
Changed paths:
M instructionAPI/src/decoder/riscv/decoder.C
Log Message:
-----------
CS_MODE_RISCVC -> CS_MODE_RISCV_C
Commit: 7a038c215e32efac74f749e7c53bb8549e04f39d
https://github.com/dyninst/dyninst/commit/7a038c215e32efac74f749e7c53bb8549e04f39d
Author: Tim Haines <[email protected]>
Date: 2026-02-06 (Fri, 06 Feb 2026)
Changed paths:
M instructionAPI/src/decoder/riscv/decoder.C
Log Message:
-----------
Add placeholders for RISCV_OP_FP, RISCV_OP_CSR
Compare:
https://github.com/dyninst/dyninst/compare/3e4a0687ed84%5E...7a038c215e32
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