We have already answered this question through formal means. We don't support 32-bit drivers for i40e at this time.
Todd Fujinaka Software Application Engineer Networking Division (ND) Intel Corporation todd.fujin...@intel.com (503) 712-4565 -----Original Message----- From: Santosh Jodh [mailto:santosh.j...@citrix.com] Sent: Friday, September 26, 2014 4:36 PM To: e1000-devel@lists.sourceforge.net Subject: [E1000-devel] i40e/i40evf Hello, I am trying to use latest i40e (1.0.15) driver from sourceforge.net (Intel XL710 SRIOV NIC) and found out that things don't work if there is an architecture mismatch between the PF and the VF (PF 32 bits, VF 64 bits for e.g.). I get messages like below when the VF driver loads: [169274.794016] i40evf: Intel(R) XL710/X710 Virtual Function Network Driver - version 1.0.5 [169274.794022] Copyright (c) 2013 - 2014 Intel Corporation. [169274.906935] i40evf 0000:00:05.0: Multiqueue Enabled: Queue pair count = 4 [169274.907383] i40evf 0000:00:05.0: MAC address: ee:b0:a6:26:08:08 [169274.907387] i40evf 0000:00:05.0: GRO is enabled [169274.907390] i40evf 0000:00:05.0: Intel(R) XL710/X710 Virtual Function Network Driver [169274.925319] systemd-udevd[18491]: renamed network interface eth1 to ens5 [169274.942523] IPv6: ADDRCONF(NETDEV_UP): ens5: link is not ready [169274.983468] i40evf 0000:00:05.0: i40evf_virtchnl_completion: PF returned error -5 to our request 6 [169275.003418] IPv6: ADDRCONF(NETDEV_CHANGE): ens5: link becomes ready [169275.105660] i40evf 0000:00:05.0: PF reset warning received [169275.105665] i40evf 0000:00:05.0: Scheduling reset task [169275.890464] i40evf 0000:00:05.0: i40evf_virtchnl_completion: PF returned error -5 to our request 6 [169276.629905] i40evf 0000:00:05.0: PF reset warning received [169276.629909] i40evf 0000:00:05.0: Scheduling reset task Is this a known issue? This seems to be due to unpacked structures shared between PF and VF in i40e_virtchannel.h [169274.983468] i40evf 0000:00:05.0: i40evf_virtchnl_completion: PF returned error -5 to our request 6 If I add following to pack the structures, I can get 32 bit PF working with both 32 bit and 64 bit VF (after recompiling both PF and VF drivers). --- i40evf-1.0.5/src/i40evf/i40e_virtchnl.h2014-07-07 10:58:05.000000000 -0700 +++ i40evf-1.0.5.new/src/i40evf/i40e_virtchnl.h2014-09-24 +++ 10:25:37.620000000 -0700 @@ -29,6 +29,8 @@ #include "i40e_type.h" +#pragma pack(push, 1) + /* Description: * This header file describes the VF-PF communication protocol used * by the various i40e drivers. @@ -363,4 +365,6 @@ enum i40e_vfr_states { I40E_VFR_UNKNOWN, }; +#pragma pack(pop) + #endif /* _I40E_VIRTCHNL_H_ */ Regards, Santosh ------------------------------------------------------------------------------ Meet PCI DSS 3.0 Compliance Requirements with EventLog Analyzer Achieve PCI DSS 3.0 Compliant Status with Out-of-the-box PCI DSS Reports Are you Audit-Ready for PCI DSS 3.0 Compliance? Download White paper Comply to PCI DSS 3.0 Requirement 10 and 11.5 with EventLog Analyzer http://pubads.g.doubleclick.net/gampad/clk?id=154622311&iu=/4140/ostg.clktrk _______________________________________________ E1000-devel mailing list E1000-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/e1000-devel To learn more about Intel® Ethernet, visit http://communities.intel.com/community/wired ------------------------------------------------------------------------------ Meet PCI DSS 3.0 Compliance Requirements with EventLog Analyzer Achieve PCI DSS 3.0 Compliant Status with Out-of-the-box PCI DSS Reports Are you Audit-Ready for PCI DSS 3.0 Compliance? Download White paper Comply to PCI DSS 3.0 Requirement 10 and 11.5 with EventLog Analyzer http://pubads.g.doubleclick.net/gampad/clk?id=154622311&iu=/4140/ostg.clktrk _______________________________________________ E1000-devel mailing list E1000-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/e1000-devel To learn more about Intel® Ethernet, visit http://communities.intel.com/community/wired
