David,
I think I have a pretty clear idea of what is going on now and why things
aren't working in MSI-X mode. Now I just need to figure out why this is
happening.
Below is the dump of the MSIXBM registers you provided with your dmesg output.
The obvious issue is that there is nothing mapping any of the queues or the
link status change to any of the msix interrupts.
igb: eth4: igb_open: MSIXBM(0): 0x00000000
igb: eth4: igb_open: MSIXBM(1): 0x00000000
igb: eth4: igb_open: MSIXBM(2): 0x00000000
igb: eth4: igb_open: MSIXBM(3): 0x00000000
igb: eth4: igb_open: MSIXBM(4): 0x00000000
What we should be seeing here is something like:
igb: eth4: igb_open: MSIXBM(0): 0x00000101
igb: eth4: igb_open: MSIXBM(1): 0x00000202
igb: eth4: igb_open: MSIXBM(2): 0x00000404
igb: eth4: igb_open: MSIXBM(3): 0x00000808
igb: eth4: igb_open: MSIXBM(4): 0x80000000
Below/attached is one more debug patch I would like you to try, and then send
me the dmesg output from. It will essentially verify if the driver is writing
these registers with the correct values or not, and if those writes are being
stored.
Thanks,
Alex
diff -urp a/src/igb_main.c b/src/igb_main.c
--- a/src/igb_main.c 2008-12-01 09:03:06.000000000 -0800
+++ b/src/igb_main.c 2008-12-01 09:58:03.000000000 -0800
@@ -373,7 +373,11 @@ static void igb_assign_vector(struct igb
adapter->tx_ring[tx_queue].eims_value =
E1000_EICR_TX_QUEUE0 << tx_queue;
}
+ DPRINTK(PROBE, INFO, "Writing 0x%08X to MSIXBM(%d)\n", msixbm,
+ msix_vector);
E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), msix_vector, msixbm);
+ DPRINTK(PROBE, INFO, "Value after write: 0x%08X\n",
+ E1000_READ_REG(hw, E1000_MSIXBM(msix_vector)));
break;
case e1000_82576:
/* 82576 uses a table-based method for assigning vectors.-------------------------------------------------------------------------
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