Of all the gin joints in all the towns in all the world, Brandeburg, Jesse had
to walk into mine and say:
> Bill Paul wrote:
> > The ixgbe_reset_hw_82598() function in ixgbe_82598.c contains the
> > following code:
> >
> > gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
> > gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
> > IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
>
> <snip>
>
> > There's just one problem: neither the register, nor the meaning of
> > those magic bits, is documented anywhere. The manual makes no mention
> > of GHECCR or offset 0x110B0, and the Intel driver code just lists it
> > under the heading of diagnostic registers.
> >
> > I really want to know what this register does (mainly so that I can
> > understand the nature of the weird behavior I was seeing before I
> > updated it), and why Intel chose not to document it in the 82598
> > manual, given that it seems to be so important to the correct
> > operation of the chip. Can any Intel people shed some light on this?
>
> Hey Bill, sorry to hear about your issue
>
> in short, the issue is a documented errata (the list doesn't allow
> attachments, so you'll get the attachment but no one else will) having
> to do with ECC being enabled on areas of on chip memory where it should
> not be, the errata causes corrupted internal memory when ECC is on, so
> that explains the behavior you've seen.
>
> Hope this helps, I suggest you go through the other errata and make sure
> those workarounds are there.
>
> Jesse
>
> PS this document is posted at intel.com but the web site has reorganized
> and that doc has disappeared for the moment. It will be fixed soon,
> I've already notified the appropriate parties.
Thanks for the reply and the manual. Now at least I know what's going on. I'd
been able to find the original 82598 manual on developer.intel.com (thanks to
google), but the spec update eluded me.
The thing is, this specification update document alone is inadequate given
that the original 82598 manual doesn't document the existence of the GHECCR
register. It says:
10. ECC On The Descriptor Completion Memory Needs To Be Disabled
Problem: Data errors can occur in Completion Memory when ECC is enabled
and an ECC error
occurs (byte enable memory does not support ECC).
Implication: Data can have errors, if enabled.
Workaround: Disable ECC on this memory area (GHECCR bits 21,18,9,6).
Status: No Fix: There are no plans to fix this erratum.
Note that it tells you about the GHECCR register, but doesn't tell you what
its offset is. Since it's not documented in the manual, the only way to
figure out how to fully implement the workaround is to refer to the Intel
sample code.
I hope there are plans to update the manual soon to correct this. (And that
means documenting all the bits in the register too.)
-Bill
--
=============================================================================
-Bill Paul (510) 749-2329 | Senior Engineer, Master of Unix-Fu
[email protected] | Wind River Systems
=============================================================================
"I put a dollar in a change machine. Nothing changed." - George Carlin
=============================================================================
------------------------------------------------------------------------------
Apps built with the Adobe(R) Flex(R) framework and Flex Builder(TM) are
powering Web 2.0 with engaging, cross-platform capabilities. Quickly and
easily build your RIAs with Flex Builder, the Eclipse(TM)based development
software that enables intelligent coding and step-through debugging.
Download the free 60 day trial. http://p.sf.net/sfu/www-adobe-com
_______________________________________________
E1000-devel mailing list
[email protected]
https://lists.sourceforge.net/lists/listinfo/e1000-devel
