Hi. I have server with 2 internal 80003ES2LAN ports and additional Intel pro/1000 PT quad port adapter (4x82571EB). # lspci | grep Ether 05:00.0 Ethernet controller: Intel Corporation 82571EB Gigabit Ethernet Controller (Copper) (rev 06) 05:00.1 Ethernet controller: Intel Corporation 82571EB Gigabit Ethernet Controller (Copper) (rev 06) 06:00.0 Ethernet controller: Intel Corporation 82571EB Gigabit Ethernet Controller (Copper) (rev 06) 06:00.1 Ethernet controller: Intel Corporation 82571EB Gigabit Ethernet Controller (Copper) (rev 06) 07:00.0 Ethernet controller: Intel Corporation 80003ES2LAN Gigabit Ethernet Controller (Copper) (rev 01) 07:00.1 Ethernet controller: Intel Corporation 80003ES2LAN Gigabit Ethernet Controller (Copper) (rev 01)
Kernel 2.6.31, driver e1000e 1.0.2.5-NAPI compiled with -DCONFIG_E1000E_SEPARATE_TX_HANDLER As I understood from README and source, there must be 3 interrupts per port, but actually there is only 1 per port: grep eth /proc/interrupts: 54: 16037 23959 15932 16014 16057 19632 4150 16247 PCI-MSI-edge eth11 55: 16059 93 15976 15935 16004 31869 16099 15996 PCI-MSI-edge eth10 56: 16122 13946 16092 28996 15976 5007 15788 16099 PCI-MSI-edge eth13 57: 16147 16043 16057 52 16037 15955 15848 31889 PCI-MSI-edge eth12 58: 87000 80692 86989 89862 87788 94201 82532 85748 PCI-MSI-edge eth20 59: 182 15800 15993 15945 31688 16064 16114 16239 PCI-MSI-edge eth21 After full boot and all interfaces up there is dmesg: # dmesg | grep e1000e e1000e: Intel(R) PRO/1000 Network Driver - 1.0.2.5-NAPI e1000e: Copyright(c) 1999 - 2009 Intel Corporation. e1000e 0000:05:00.0: PCI INT B -> GSI 19 (level, low) -> IRQ 19 e1000e 0000:05:00.0: setting latency timer to 64 e1000e 0000:05:00.0: irq 54 for MSI/MSI-X e1000e 0000:05:00.1: PCI INT A -> GSI 18 (level, low) -> IRQ 18 e1000e 0000:05:00.1: setting latency timer to 64 e1000e 0000:05:00.1: irq 55 for MSI/MSI-X e1000e 0000:06:00.0: PCI INT B -> GSI 17 (level, low) -> IRQ 17 e1000e 0000:06:00.0: setting latency timer to 64 e1000e 0000:06:00.0: irq 56 for MSI/MSI-X e1000e 0000:06:00.1: PCI INT A -> GSI 16 (level, low) -> IRQ 16 e1000e 0000:06:00.1: setting latency timer to 64 e1000e 0000:06:00.1: irq 57 for MSI/MSI-X e1000e 0000:07:00.0: PCI INT A -> GSI 18 (level, low) -> IRQ 18 e1000e 0000:07:00.0: setting latency timer to 64 e1000e 0000:07:00.0: irq 58 for MSI/MSI-X e1000e 0000:07:00.1: PCI INT B -> GSI 19 (level, low) -> IRQ 19 e1000e 0000:07:00.1: setting latency timer to 64 e1000e 0000:07:00.1: irq 59 for MSI/MSI-X e1000e 0000:07:00.0: irq 58 for MSI/MSI-X e1000e 0000:07:00.0: irq 58 for MSI/MSI-X e1000e: eth20 NIC Link is Up 100 Mbps Full Duplex, Flow Control: None e1000e 0000:05:00.1: irq 55 for MSI/MSI-X e1000e 0000:05:00.1: irq 55 for MSI/MSI-X e1000e 0000:05:00.0: irq 54 for MSI/MSI-X e1000e 0000:05:00.0: irq 54 for MSI/MSI-X e1000e 0000:06:00.1: irq 57 for MSI/MSI-X e1000e 0000:06:00.1: irq 57 for MSI/MSI-X e1000e 0000:06:00.0: irq 56 for MSI/MSI-X e1000e 0000:06:00.0: irq 56 for MSI/MSI-X e1000e 0000:07:00.1: irq 59 for MSI/MSI-X e1000e 0000:07:00.1: irq 59 for MSI/MSI-X Seems like 1 interrupt is allocated for all 3 queues: 1 at driver load time and 2 at interface UP. Is it a bug somewhere or I am wrong and everything is OK? -- ------------------------------------------------------------------------------ Come build with us! The BlackBerry(R) Developer Conference in SF, CA is the only developer event you need to attend this year. Jumpstart your developing skills, take BlackBerry mobile applications to market and stay ahead of the curve. Join us from November 9 - 12, 2009. Register now! http://p.sf.net/sfu/devconference _______________________________________________ E1000-devel mailing list E1000-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/e1000-devel
