From: Milton Miller <[email protected]> The PowerPC architecture does not require loads to independent bytes to be ordered without adding an explicit barrier.
In ixgbe_clean_rx_irq we load the status bit then load the packet data. With packet split disabled if these loads go out of order we get a stale packet, but we will notice the bad sequence numbers and drop it. The problem occurs with packet split enabled where the TCP/IP header and data are in different descriptors. If the reads go out of order we may have data that doesn't match the TCP/IP header. Since we use hardware checksumming this bad data is never verified and it makes it all the way to the application. This bug was found during stress testing and adding this barrier has been shown to fix it. Signed-off-by: Milton Miller <[email protected]> Signed-off-by: Anton Blanchard <[email protected]> --- This was a nasty bug to hunt down, if people agree with the fix I think it's a candidate for stable. Index: work.git/drivers/net/ixgbe/ixgbe_main.c =================================================================== --- work.git.orig/drivers/net/ixgbe/ixgbe_main.c 2010-02-11 16:24:27.000000000 -0600 +++ work.git/drivers/net/ixgbe/ixgbe_main.c 2010-02-11 16:49:27.000000000 -0600 @@ -806,6 +806,7 @@ static bool ixgbe_clean_rx_irq(struct ix break; (*work_done)++; + rmb(); /* read descriptor and rx_buffer_info after status DD */ if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) { hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc)); len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >> ------------------------------------------------------------------------------ SOLARIS 10 is the OS for Data Centers - provides features such as DTrace, Predictive Self Healing and Award Winning ZFS. Get Solaris 10 NOW http://p.sf.net/sfu/solaris-dev2dev _______________________________________________ E1000-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/e1000-devel To learn more about Intel® Ethernet, visit http://communities.intel.com/community/wired
