this series of patches exposes the bandwidth allocation hardware support of
the Intel 82576. It does so through a rather hackish sysfs entry. That
interface is just intended for testing so that the exposed hardware feature
can be exercised. I would like to find a generic way to expose this feature
to user-space.

v2
* Remove the patch "Initialise adapter->vfs_allocated_count in
  igb_init_vf()" as it causes a panic.

v3
* Incorporate several suggestions from Alexander Duyck
  as noted in the per-patch changelogs


Hi,Simon
Linux2.6.32, using v3 of the patch, but it does not work.I read the 82576
v2.61 datasheet following contents:
-------------------------------------------
4.5.11.1.5 Allocation of Tx Bandwidth to VMs
4.5.11.1.5.1 Configuring Tx Bandwidth to VMs
Allocation of Tx Bandwidth to VMs feature is enabled or disabled via the
programming of VMBACS and
VMBAMMW registers. When enabled, bandwidth to VMs (i.e. to Tx Queues) is
configured via writing into
VMBASEL and VMBAC registers for each queue again.
The bandwidth configuring procedure is as follow -
1. Allocate non-null rates to VMs present in the system RVMi (i=0..7), in
Gb/s units, so that:
RVM0 + RVM1 + ... + RVM7 = 0.5 Gb/s
Assume also that for any different i,j:
RVMi / RVMj < 10 and RVMj / RVMi < 10
2. Allocate rates to enabled queues RQi (i=0..7), in Gb/s units, so that:
RQi = RQi+8 = RVMi / 2
3. Compute rate factors RFQi (i=0..15) for all the enabled Tx queues, so
that:
RFQi = 1 Gb/s / RQi
4. Format the rate factors obtained in the previous step as decimal binary
numbers, with 10-bits
integral part left of the decimal point, and 14-bits decimal part right of
it, and for i=0..15, set
RTTDQSEL.TXDQ_IDX=i and then:
a. Set RTTDVMRC.RF_INT = integral part of RFQi
b. Set RTTDVMRC.RF_DEC = decimal part of RFQi
5. Compute VM_MMW_SIZE to the VM Rate-Scheduler as follow:
VM_MMW_SIZE = 16 x MSS
for avoiding saturation while full workload. Refer to Section 4.5.11.1.5.2.
6. Set VMBAMMW.MMW_SIZE = VM_MMW_SIZE

4.5.11.1.5.2 Link Speed Change Procedure
Whenever the link status or speed is changed, the 82576 operates the VM
arbiters in a packet based
round robin mode, and disables the VM rate-controllers. Software is
responsible to re-enabling and re-
configuring them accordingly to the new link speed. However, to avoid any
race condition between
hardware and software, the following procedure must be performed by the
driver whenever a link
speed/status change interrupt occurs:
1. Check the SPEED_CHG bit in VMBACS register was asserted by hardware.
2. Read the VMBA_SET bit in the VMBACS register.
3. If the bit is read as 1, it means the VM rate-controllers were not
completely disabled by hardware
(i.e. a race occurred between hardware and software). Software must
therefore clear the RC_ENA
bit in the VMBAC register for all the queues, or for at least the queue(s)
for which it is still set.
4. Clear the SPEED_CHG bit in VMBACS register.
-----------------------------------------------------
Your code not  set VMBACS register VM Bandwidth Allocation Enable field.Is
the reason?

I found some parts of your code is duplicated.
static void igb_enable_bandwidth_allocation(struct igb_adapter *adapter)
{
...
         for (i = 0; i < adapter->vfs_allocated_count; i++) {
                *wr32(E1000_VMBASEL, i);*
                if (adapter->bandwidth_allocation[i])
                        igb_enable_bandwidth_allocation_vf(hw, i,
                                        adapter->bandwidth_allocation[i]);
                else
                        igb_disable_bandwidth_allocation_vf(hw, i);
...
}

in the igb_enable_bandwidth_allocation function used : *wr32(E1000_VMBASEL,
i);
*and igb_enable_bandwidth_allocation_vf 、igb_disable_bandwidth_allocation_vf
used *wr32(E1000_VMBASEL, i); *too*.*
------------------------------------------------------------------------------
Xperia(TM) PLAY
It's a major breakthrough. An authentic gaming
smartphone on the nation's most reliable network.
And it wants your games.
http://p.sf.net/sfu/verizon-sfdev
_______________________________________________
E1000-devel mailing list
[email protected]
https://lists.sourceforge.net/lists/listinfo/e1000-devel
To learn more about Intel&#174; Ethernet, visit 
http://communities.intel.com/community/wired

Reply via email to