Hi Alex,
Thanks, the register "Queue Packets Received Drop Count — QPRDC" which
updates that stat seems to be what Im looking for.
Regards
Jonathan
On 7 July 2011 18:44, Alexander Duyck <[email protected]> wrote:
> If the DROP_EN bit is set you should see the rx_no_dma_resources counter
> start to increment if packets are being dropped due to a lack of DMA
> resources.
>
> Thanks,
>
> Alex
>
>
> On 07/07/2011 10:04 AM, Lynch, Jonathan wrote:
>
>> Hi Alex,
>>
>> If SRRCTL.DROP_EN happens to be set, is there any other register which
>> counts the packets which are "dropped at the head of the FIFO for not having
>> a free descriptor." ?
>>
>> Thanks
>> Jonathan
>>
>> On 7 July 2011 16:57, Alexander Duyck <[email protected]<mailto:
>> alexander.h.duyck@**intel.com <[email protected]>>> wrote:
>>
>> On 07/06/2011 03:40 AM, Lynch, Jonathan wrote:
>>
>> Hi Alex,
>>
>> Quick question on when RXMPC is incremented on 82599 hardware.
>> Does the hardware check if RDH[n] == RDT[n]. If this is true
>> there are no descriptors free, hence packet dropped, RXMPC[n]++?
>>
>> 8.2.3.23.4 Rx Missed Packets Count — RXMPC[n] (0x03FA0 + 4*n,
>> n=0...7; RC) DBU-Rx
>> Register ‘n’ counts the number of missed packets per packet
>> buffer ‘n’.
>> Packets are missed when the receive FIFO has insufficient
>> space to store the incoming
>> packet. This may be caused due to insufficient buffers
>> allocated, or because there is
>> insufficient bandwidth on the IO bus. Events setting this
>> counter also set the receiver
>> overrun interrupt (RXO). These registers do not increment if
>> receive is not enabled and
>> count only packets that would have been posted to the SW driver.
>>
>> Regards
>> Jonathan
>>
>>
>> RXMPC is incremented any time the RX FIFO is filled and a packet
>> is received that cannot be placed on the FIFO. It does not check
>> RDH/RDT values. There are two ways to end up with the RX FIFO
>> being filled.
>>
>> The first way to fill the RX FIFO is if the software cannot keep
>> up. This results in the RDH[n] == RDT[n] scenerio that you
>> described above, but what this triggers is packets to start
>> waiting in the RX FIFO for free space. In order for this to occur
>> you also need to have the SRRCTL.DROP_EN bit cleared in order to
>> prevent the packet from being dropped at the head of the FIFO for
>> not having a free descriptor.
>>
>> The second way to fill the RX FIFO is if the PCIe bus is somehow
>> limited and cannot move the packets from the RX FIFO into the
>> system memory fast enough. This can happen if for example you are
>> on a x4 or smaller PCIe link, or possibly on a PCIe gen 1 link.
>>
>> Thanks,
>>
>> Alex
>>
>>
>>
>
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