On Mon, 24 Oct 2011 23:29:34 -0700 Michael Wang <wang...@linux.vnet.ibm.com> wrote: > May be you can just search macro > "E1000_TXDCTL_DMA_BURST_ENABLE" > in "drivers/net/e1000e/e1000.h", change it to: > > #define E1000_TXDCTL_DMA_BURST_ENABLE \ > (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \ > E1000_TXDCTL_COUNT_DESC | \ > (0 << 16) | /* wthresh must be +1 more than desired */\ > (1 << 8) | /* hthresh */ \ > 0x1f) /* pthresh */ > > this will do the write-back even only one has been done, if the > problem solved, we can think about a good solution.
I can already tell you that this will fix the problem, but wthresh=1 is more like the hardware default after reset I think. Doing this will prevent the bursting behavior that got us the performance improvement this patch was made for, which is bad. That is why we are looking at a solution that likely involves two flush writes via the "flush partial descriptors" bits. Just do the bit 31 set in TIDV and RDTR twice in a row and then make sure it is write flushed. If you wish to implement that and give it a try that would be useful information. We haven't had time yet to get a full repro going. ------------------------------------------------------------------------------ The demand for IT networking professionals continues to grow, and the demand for specialized networking skills is growing even more rapidly. Take a complimentary Learning@Cisco Self-Assessment and learn about Cisco certifications, training, and career opportunities. http://p.sf.net/sfu/cisco-dev2dev _______________________________________________ E1000-devel mailing list E1000-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/e1000-devel To learn more about Intel® Ethernet, visit http://communities.intel.com/community/wired
