The minimum number of MSI-Xs is (MLX5_EQ_VEC_COMP_BASE + 1) in one check and 2 in another check. Make the checks consistent and assume the minimum number is (MLX5_EQ_VEC_COMP_BASE + 1).
Signed-off-by: Alexander Gordeev <[email protected]> --- drivers/net/ethernet/mellanox/mlx5/core/main.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c index 5e5c9a3..adf0e5d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -136,7 +136,7 @@ retry: err = pci_enable_msix(dev->pdev, table->msix_arr, nvec); if (err <= 0) { return err; - } else if (err > 2) { + } else if (err > MLX5_EQ_VEC_COMP_BASE) { nvec = err; goto retry; } -- 1.7.7.6 ------------------------------------------------------------------------------ October Webinars: Code for Performance Free Intel webinars can help you accelerate application performance. Explore tips for MPI, OpenMP, advanced profiling, and more. Get the most from the latest Intel processors and coprocessors. See abstracts and register > http://pubads.g.doubleclick.net/gampad/clk?id=60134791&iu=/4140/ostg.clktrk _______________________________________________ E1000-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/e1000-devel To learn more about Intel® Ethernet, visit http://communities.intel.com/community/wired
