Thanks Alex,
This issue seems irrespective of whether DLP bit is set or not as somehow I
don't see this bit set now but issue still persists.
In fact, I see this even when none of uncorrectable AER bit is set.
On Tue, May 6, 2014 at 2:50 AM, Alexander Duyck <alexander.h.du...@intel.com
> wrote:
> On 05/05/2014 01:38 PM, Thomas Petazzoni wrote:
> > Dear Alexander Duyck,
> >
> > On Mon, 05 May 2014 08:28:02 -0700, Alexander Duyck wrote:
> >
> >>> 1. So overall issue is any memory/config space access hangs(logs above)
> >>> if bus master enable bit is set on IGB NIC card,this is not observed
> >>> with E1000E NIC cards on same platform.
> >>>
> >>> 2. Above issue is repro'able on my ARM platform, not x86 ubuntu. Not
> >>> sure how much its related to ARM though.
> >>>
> >>> 3. I saw below differences in lspci -vvv output b/w e1000e and igb, I
> am
> >>> not sure if this has anything to do with above issue.
> >>> RC config is same for both cases.
> >>>
> >>> IGB / E1000E
> >>>
> >>> Command Status: INTx+/INTx-
> >>> PM Status: NoSoftRst+/NoSoftRst-
> >>> DevCap: FLReset-/FLReset+
> >>> No Dev/Link2 Cap/Sta Registers for E1000E
> >>> Some differences in AER Registers
> >>>
> >>> 4. Any idea, if this card is verified on ARM by anybody?
> >>>
> >>
> >> It seems like you are glossing over the obvious issue. You said it
> >> yourself, this works fine on x86. Therefore this is likely VERY related
> >> to ARM, or at least your specific ARM platform configuration.
> >
> > Since I haven't seen the beginning of the thread, I might be completely
> > off topic. However, I wanted to mention that I have successfully used
> > and tested an IGB PCIe NIC on an ARM Armada XP platform. If that is
> > useful, I'd be happy to provide you with additional details upon
> > request.
> >
> > Best regards,
> >
> > Thomas
> >
>
>
> Thomas,
>
> Glad to hear that this is working on your ARM platform as expected.
>
> I believe the issue Shiv is having is due to a problem with the specific
> platform as the IGB device is reporting a Data Link Protocol error via
> AER and I believe this is what is causing his platform issues. On
> enabling BME the device is likely signalling a Fatal Error message in
> response to the DLP error. The original error he was seeing was:
>
> Unhandled fault: imprecise external abort (0x1406) at 0x00000000
>
> Thanks,
>
> Alex
>
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