Hi, On Mon, 16 Feb 2009 13:48:22 +0100, Chris Zimman <czim...@bloomberg.com> wrote:
>> Is the FIQ interrupt disabled while scheduling? (And if so - is it >> disabled that long time?) I hope it isn't ... >> The only RT requirement is to read the data from the memory bus >> 12us after the interrupt at the latest. The processing afterwards >> can be done in non-RT. > > Interrupts have to be disabled while you're in an ISR, and since the > scheduler is typically driven from a timer interrupt, you are going to run > into that. There is an option to allow nested interrupts. Since the FIQ priority is higher than that of the timer (typical priority 0) it would interrupt it. > Not being familiar with your project, I can't really say, but if I were to > design something that needed this level of RT performance, I would probably > use a faster processor or a small CPLD/FPGA to help with the data > acquisition. There is a cpld already do deserialize the data. However - it has not enought flipflops/macrocells to provide a buffer. (And no external or dualport memory.) I will try the FIQ and nested interrupt aproach this evening and report the results. Greetings, Martin L.
