Hello again W dniu 2011-03-28 12:47:07 użytkownik jerzy dyrda <jer...@gmail.com> napisał: > Hello all, > > On Monday 28 March 2011 11:51:45 qb...@poczta.onet.pl wrote: > (...) > > There is only one thing left - the RCC differences. In RM there is a > > seperate section about RCC config for CL. But at the first look it seems > > that registers are compatible. > RCC registers are extended to support 2 extra PPL's with appropriate divider > and multiplier. > Main differences is that source of PLL clock it isn't anymore taken directly > from HSE or HSE/2 clock > but it's introduced new divider PREDIV1 thus PLLSRC bit in RCC_CFGR register > has partially > different meaning. And another issue is external crystal. It value is 25MHz > not 8 MHz like in > STM3210E what causes need of using second PLL to produce CPU 72MHz. > > HSE == 25MHz / PREDIV2 == 5 -> 5MHz * PLLMUL2 == 8 -> > 40MHz / PREDIV1 == 5 -> 8MHz * PLLMUL == 9 -> 72MHz = SYSCLK > > It's looks ugly but above method it's used in ST source code for STM3210C > evaluation board. >
It's not quite true. According to scheme and RM the clock can be takien from PLL2 or HSE directly. This is configured in RCC_CFGR2 bit 16 PREDIV1_SRC. Only the crystal have to be replaced on PCB. > Best regards > jerzy > > Best regards Qber
