Andrey Baboshin wrote:
Hi, all.I find following problem. I enable the MMU in eCos and it executes next code # Initialize MMU. bl hal_MMU_init # Enable MMU (if desired) so we can safely enable caches. lwi r3,CYG_MSR # interrupts enabled later sync mtmsr r3 (*) sync # Enable caches bl hal_enable_caches I have found it fails after (*). In additional CYG_MSR = (CYG_MSR_COMMON | IP_BIT | IR_DR_BITS) CYG_MSR_COMMON = (MSR_FP | MSR_ME | MSR_RI) IP_BIT = 0 IR_DR_BITS = (MSR_IR | MSR_DR) Do have anyone some problem? It works only when I comment mtmsr r3 and followed by it sync.
Which only means that it works with the MMU turned off :-( How did you setup the MMU? What target/platform are you working with? -- ------------------------------------------------------------ Gary Thomas | Consulting for the MLB Associates | Embedded world ------------------------------------------------------------ -- Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss
