On 07.04.2013 14:06, Randy wrote:
> After one ISR is over, the DSRs in FIFO queue starts to run one by
> one like A=>B=>C=>... If one interrupt comes when B is running, then
> what will happen? If B is stoped and the new ISR is going to run,
> then, how and when does the B come back(we may cann't use
> "reschedule" to describe it)?
The processor detects the interrupt, saves the current program
counter on the stack, looks up the table defining wich handler
is to be run for tha particular interupt source and runs the
handler.
When this handler returns, then whatever the handler interrupted
will continue where it was interrupted, in this case B.
The exact sequence of steps is hardware- and configuration-dependent,
the interrupt and exception handling is where the architectures
differ significantly.
> Or, could you tell me which code snippet in eCos3.0 shows the handler?
This is architecture specific partly assembler code. Look for
vectors.S and other files in your HAL, but you will only
understand it if you have quite detailed knowledge about your
processor. I never needed to go that deep.
Regards
--
Stano
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