On Wed, Feb 08, 2006 at 11:24:49AM +0000, Nick Garnett wrote:
> Andrew Lunn <[EMAIL PROTECTED]> writes:
> 
> > On Mon, Feb 06, 2006 at 08:58:05PM +0300, Sergei Organov wrote:
> > > Jay Foster <[EMAIL PROTECTED]> writes:
> > > > Revised patch attached.
> > > 
> > > The patch looks OK to me, but I don't see it applied to the public CVS
> > > :(
> > 
> > Is the general consensue that this patch is OK now? If so i will
> > commit it.
> 
> Yes, it looks OK. At least it will do no harm.

OK. 

Applied.

        Andrew
Index: ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/arch/current/ChangeLog,v
retrieving revision 1.104
diff -u -r1.104 ChangeLog
--- ChangeLog   21 Apr 2005 18:17:54 -0000      1.104
+++ ChangeLog   8 Feb 2006 12:06:15 -0000
@@ -1,3 +1,8 @@
+2006-01-18  Jay Foster    <[EMAIL PROTECTED]>
+
+       * src/context.S (hal_thread_switch_context): Close race condition
+       that could cause corruption of the sp or lr registers.
+
 2005-04-21  Ian Campbell  <[EMAIL PROTECTED]>
 
        * src/redboot_linux_exec.c: Added -t option which takes the
Index: src/context.S
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/arch/current/src/context.S,v
retrieving revision 1.9
diff -u -r1.9 context.S
--- src/context.S       23 May 2002 23:01:42 -0000      1.9
+++ src/context.S       8 Feb 2006 12:06:15 -0000
@@ -89,12 +89,13 @@
 // Need to save/restore R4..R12, R13 (sp), R14 (lr)
 
 // Note: this is a little wasteful since r0..r3 don't need to be saved.
-// They are saved here though so that the information can match the 
HAL_SavedRegisters
+// They are saved here though so that the information can match the
+// HAL_SavedRegisters
         
 FUNC_START_ARM(hal_thread_switch_context, r2)
-        sub     ip,sp,#20               // skip svc_sp, svc_lr, vector, cpsr, 
and pc
-        stmfd   ip!,{sp,lr}
-        mov     sp,ip
+        mov     ip,sp
+        sub     sp,sp,#(ARMREG_SIZE - armreg_lr - 4) // skip svc_sp, svc_lr, 
vector, cpsr, and pc
+        stmfd   sp!,{ip,lr}
         stmfd   sp!,{r0-r10,fp,ip}
         mrs     r2,cpsr
         str     r2,[sp,#armreg_cpsr]

Reply via email to