On Mon, Feb 06, 2006 at 09:30:27PM +0300, Sergei Organov wrote:
> The patch below disables FIQ in IRQ handler to fix race condition
> that may result in recursive entry into IRQ handler through FIQ
> handler.

Applied, with updated comment.

        Andrew

Index: hal/arm/arch/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/arch/current/ChangeLog,v
retrieving revision 1.105
diff -u -r1.105 ChangeLog
--- hal/arm/arch/current/ChangeLog      8 Feb 2006 12:06:38 -0000       1.105
+++ hal/arm/arch/current/ChangeLog      9 Feb 2006 16:46:29 -0000
@@ -1,3 +1,9 @@
+2006-02-06  Sergei Organov  <[EMAIL PROTECTED]>
+
+       * src/vectors.S: disable FIQ in IRQ handler to fix race condition
+       of recursively entering IRQ handler through FIQ handler. Remove
+       unreferenced handle_IRQ_or_FIQ label.
+       
 2006-01-18  Jay Foster    <[EMAIL PROTECTED]>
 
        * src/context.S (hal_thread_switch_context): Close race condition
Index: hal/arm/arch/current/src/vectors.S
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/arch/current/src/vectors.S,v
retrieving revision 1.55
diff -u -r1.55 vectors.S
--- hal/arm/arch/current/src/vectors.S  23 Nov 2004 14:11:19 -0000      1.55
+++ hal/arm/arch/current/src/vectors.S  9 Feb 2006 16:46:31 -0000
@@ -787,11 +787,16 @@
         mov     r2,#CYGNUM_HAL_VECTOR_IRQ
         mov     r3,sp
        
-handle_IRQ_or_FIQ:
-
         mrs     r4,cpsr                 // switch to Supervisor Mode
         bic     r4,r4,#CPSR_MODE_BITS
-        orr     r4,r4,#CPSR_SUPERVISOR_MODE
+        // When handling an IRQ we must disable FIQ unless the current 
+        // mode in CPSR is IRQ. If we were to get a FIQ while in another 
+        // mode, the FIQ handling code would transform the FIQ into an 
+        // IRQ and call the non-reentrant IRQ handler again. As a result, 
+        // for example, the stack pointer would be set to the beginning 
+        // of the exception_stack clobbering the registers we have just 
+        // saved.
+        orr     r4,r4,#CPSR_SUPERVISOR_MODE|CPSR_FIQ_DISABLE
         msr     cpsr,r4
 
         mov     r5,sp                   // save original svc sp

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