Submitted for your approval. This patch adds support for the ARM926EJ, the
ARM processor in the OMAP 5912, and fixes a problem with the CLEAN DCACHE
code for the ARM925T.
The copyright assignment for DTC Communications has been previously
submitted.
Paul Fine
Principal Digital Communications Software Engineer
DTC Communications, Inc.
Index: hal/arm/arm9/var/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/arm9/var/current/ChangeLog,v
retrieving revision 1.7
diff -u -5 -p -r1.7 ChangeLog
--- hal/arm/arm9/var/current/ChangeLog 8 Jan 2003 19:47:34 -0000 1.7
+++ hal/arm/arm9/var/current/ChangeLog 17 Feb 2006 20:57:14 -0000
@@ -1,5 +1,15 @@
+2006-02-17 Tom Chase <[EMAIL PROTECTED]>
+
+ * include/hal_cache.h: Added support for ARM926EJ. Changed
+ ARM925T to use CYGHWR_HAL_ARM_ARM9_ALT_CLEAN_CACHE and defined
+ CYGHWR_HAL_ARM_ARM9_ALT_CLEAN_CACHE to clean the cache manually
+ because CYGHWR_HAL_ARM_ARM9_CLEAN_CACHE did not work for the
+ OMAP1510.
+
+ * cdl/hal_arm_arm9.cdl: Added option for ARM926EJ.
+
2003-01-08 Patrick Doyle <[EMAIL PROTECTED]>
* include/hal_cache.h: Changed HAL_ICACHE_LINE_SIZE and
HAL_DCACHE_LINE_SIZE to match the documentation from TI. Now the
kcache2 test passes the two tests that it runs.
Index: hal/arm/arm9/var/current/cdl/hal_arm_arm9.cdl
===================================================================
RCS file:
/cvs/ecos/ecos/packages/hal/arm/arm9/var/current/cdl/hal_arm_arm9.cdl,v
retrieving revision 1.4
diff -u -5 -p -r1.4 hal_arm_arm9.cdl
--- hal/arm/arm9/var/current/cdl/hal_arm_arm9.cdl 23 May 2002 23:01:46
-0000 1.4
+++ hal/arm/arm9/var/current/cdl/hal_arm_arm9.cdl 17 Feb 2006 20:57:14
-0000
@@ -104,10 +104,21 @@ cdl_package CYGPKG_HAL_ARM_ARM9 {
define -file=system.h CYGPKG_HAL_ARM_ARM9_ARM925T
description "
The ARM925T has 8k data cache, 16k instruction cache, 16 word
write buffer and an MMU."
}
+
+ cdl_option CYGPKG_HAL_ARM_ARM9_ARM926EJ {
+ display "ARM ARM926EJ microprocessor"
+ implements CYGINT_HAL_ARM_ARM9_VARIANT
+ default_value 0
+ no_define
+ define -file=system.h CYGPKG_HAL_ARM_ARM9_ARM926EJ
+ description "
+ The ARM926EJ has 16k data cache, 16k instruction cache, 16 word
+ write buffer and an MMU."
+ }
cdl_option CYGPKG_HAL_ARM_ARM9_ARM940T {
display "ARM ARM940T microprocessor"
implements CYGINT_HAL_ARM_ARM9_VARIANT
default_value 0
Index: hal/arm/arm9/var/current/include/hal_cache.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/arm9/var/current/include/hal_cache.h,v
retrieving revision 1.7
diff -u -5 -p -r1.7 hal_cache.h
--- hal/arm/arm9/var/current/include/hal_cache.h 8 Jan 2003 19:47:37
-0000 1.7
+++ hal/arm/arm9/var/current/include/hal_cache.h 17 Feb 2006 20:57:14
-0000
@@ -44,11 +44,12 @@
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors:hmt, jskov
// Travis C. Furrer <[EMAIL PROTECTED]>
-// Date: 2000-05-08
+// Tom Chase <[EMAIL PROTECTED]>
+// Date: 2005-05-10
// Purpose: Cache control API
// Description: The macros defined here provide the HAL APIs for handling
// cache control operations.
// Usage:
// #include <cyg/hal/hal_cache.h>
@@ -110,12 +111,27 @@
# define HAL_DCACHE_LINE_SIZE 16
# define HAL_DCACHE_WAYS 2
# define HAL_DCACHE_SETS
(HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
# define HAL_WRITE_BUFFER 64
+// must flush everything manually
+# define CYGHWR_HAL_ARM_ARM9_ALT_CLEAN_DCACHE
-# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE // has instruction to clean D-cache
+#elif defined(CYGPKG_HAL_ARM_ARM9_ARM926EJ)
+# define HAL_ICACHE_SIZE 0x4000
+# define HAL_ICACHE_LINE_SIZE 32
+# define HAL_ICACHE_WAYS 4
+# define HAL_ICACHE_SETS
(HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
+
+# define HAL_DCACHE_SIZE 0x2000
+# define HAL_DCACHE_LINE_SIZE 32
+# define HAL_DCACHE_WAYS 4
+# define HAL_DCACHE_SETS
(HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
+
+# define HAL_WRITE_BUFFER 64
+
+#define CYGHWR_HAL_ARM_ARM926EJ_CLEAN_DCACHE //has instruction to clean D-cache
#elif defined(CYGPKG_HAL_ARM_ARM9_ARM940T)
# define HAL_ICACHE_SIZE 0x1000
# define HAL_ICACHE_LINE_SIZE 16
# define HAL_ICACHE_WAYS 4
@@ -367,10 +383,44 @@ CYG_MACRO_START
: "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP), \
"I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT) \
: "r0" /* Clobber list */ \
); \
CYG_MACRO_END
+#elif defined(CYGHWR_HAL_ARM_ARM9_ALT_CLEAN_DCACHE)
+/*
+ * 'Clean & Invalidate whole DCache'
+ */
+#define HAL_DCACHE_SYNC() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "mov r0, #255 << 4;" /* 256 entries/set */ \
+ "2: " \
+ "mcr p15, 0, r0, c7, c14, 2;" \
+ "subs r0, r0, #1 << 4;" \
+ "bcs 2b;" /* entries 255 to 0 */ \
+ "mcr p15,0,r0,c7,c10,4;" /* drain the write buffer */ \
+ : \
+ : \
+ : "r0" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
+#elif defined(CYGHWR_HAL_ARM_ARM926EJ_CLEAN_DCACHE)
+/*
+ * 'Clean & Invalidate whole DCache'
+ */
+#define HAL_DCACHE_SYNC() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "1: " /* clean & invalidate D index */ \
+ "mrc p15, 0, r15, c7, c14, 3;" \
+ "bne 1b;" \
+ "mcr p15,0,r0,c7,c10,4;" /* drain the write buffer */ \
+ : \
+ : \
+ : "r0" /* Clobber list */ \
+ ); \
+CYG_MACRO_END
#else
# error "Don't know how to sync Dcache"
#endif
#else
