Hi Folks
This patch from Oliver Munz allows the AT91SAM7S Debug UART to be used
as a noral USART. The debug UART ha most of the functionality of the
normal USART, so only less well used features, like changing the
start/stop bits & parity will not work for the debug UART.
This patch also changes the PLL settings again to values that really
do with the USB device.
Andrew
Index: devs/serial/arm/at91/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/serial/arm/at91/current/ChangeLog,v
retrieving revision 1.14
diff -u -r1.14 ChangeLog
--- devs/serial/arm/at91/current/ChangeLog 1 Mar 2006 18:13:44 -0000
1.14
+++ devs/serial/arm/at91/current/ChangeLog 13 Mar 2006 07:44:01 -0000
@@ -1,3 +1,8 @@
+2006-03-05 Oliver Munz <[EMAIL PROTECTED]>
+
+ * src/at91_serial.c (at91_serial_ISR): Only call the DSR if there
+ is work to do.
+
2006-02-28 Andrew Lunn <[EMAIL PROTECTED]>
Oliver Munz <[EMAIL PROTECTED]>
Index: devs/serial/arm/at91/current/src/at91_serial.c
===================================================================
RCS file:
/cvs/ecos/ecos/packages/devs/serial/arm/at91/current/src/at91_serial.c,v
retrieving revision 1.12
diff -u -r1.12 at91_serial.c
--- devs/serial/arm/at91/current/src/at91_serial.c 1 Mar 2006 18:13:44
-0000 1.12
+++ devs/serial/arm/at91/current/src/at91_serial.c 13 Mar 2006 07:44:02
-0000
@@ -524,7 +524,8 @@
at91_serial_info * const at91_chan = (at91_serial_info *) chan->dev_priv;
const CYG_ADDRWORD base = at91_chan->base;
CYG_WORD32 stat, mask;
-
+ cyg_uint32 retcode = 0;
+
HAL_READ_UINT32(base + AT91_US_CSR, stat);
HAL_READ_UINT32(base + AT91_US_IMR, mask);
stat &= mask;
@@ -540,14 +541,17 @@
(CYG_ADDRESS) at91_chan->rcv_buffer[at91_chan->curbuf]
+ at91_chan->rcv_chunk_size + RCVBUF_EXTRA - x
);
+ retcode = CYG_ISR_CALL_DSR;
}
- if (stat & (AT91_US_IER_TxRDY | AT91_US_IER_ENDTX))
+ if (stat & (AT91_US_IER_TxRDY | AT91_US_IER_ENDTX)) {
HAL_WRITE_UINT32(base + AT91_US_IDR, AT91_US_IER_TxRDY |
AT91_US_IER_ENDTX);
-
+ retcode = CYG_ISR_CALL_DSR;
+ }
at91_chan->stat |= stat;
+
cyg_drv_interrupt_acknowledge(vector);
- return CYG_ISR_CALL_DSR;
+ return retcode;
}
// Serial I/O - high level interrupt handler (DSR)
Index: hal/arm/at91/at91sam7s/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/ChangeLog,v
retrieving revision 1.4
diff -u -r1.4 ChangeLog
--- hal/arm/at91/at91sam7s/current/ChangeLog 1 Mar 2006 20:43:18 -0000
1.4
+++ hal/arm/at91/at91sam7s/current/ChangeLog 13 Mar 2006 07:44:02 -0000
@@ -1,3 +1,17 @@
+2006-03-10 Oliver Munz <[EMAIL PROTECTED]>
+
+ * hal_arm_at91sam7s.cdl: Change the PLL-defaults so that 96MHz is
+ generated so that the USB does work.
+
+2006-03-10 Andrew Lunn <[EMAIL PROTECTED]>
+ Oliver Munz <[EMAIL PROTECTED]>
+
+ * cdl/hal_arm_at91sam7s.cdl: Set the debug UART as the default
+ channel and fix some dodge spelling.
+ * src/at91sam7s_misc.c (hal_plf_hardware_init): Enable the Debug UART
+ pins for output and control by the device.
+ * include/plf_io.h: Define USART2 to be the debug UART.
+
2006-03-01 Andrew Lunn <[EMAIL PROTECTED]>
* cdl/hal_arm_at91sam7s.cdl: Change the crystal frequency. The
Index: hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl
===================================================================
RCS file:
/cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl,v
retrieving revision 1.2
diff -u -r1.2 hal_arm_at91sam7s.cdl
--- hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl 1 Mar 2006
20:43:18 -0000 1.2
+++ hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl 13 Mar 2006
07:44:03 -0000
@@ -39,7 +39,7 @@
######DESCRIPTIONBEGIN####
#
# Author(s): gthomas
-# Contributors: gthomas, tkoeller, nickg, Oliver Munz
+# Contributors: gthomas, tkoeller, nickg, Oliver Munz, asl
# Date: 2005-06-20
#
#####DESCRIPTIONEND####
@@ -62,11 +62,11 @@
requires { CYGHWR_HAL_ARM_AT91_FIQ }
requires { CYGHWR_HAL_ARM_AT91SAM7S == "at91sam7s32" implies
CYGPKG_IO_SERIAL_ARM_AT91_SERIAL0 == 0 }
- requires { CYGPKG_IO_SERIAL_ARM_AT91_SERIAL2 == 0 }
implements CYGINT_HAL_ARM_AT91_SERIAL_DBG_HW
implements CYGINT_HAL_ARM_AT91_PIT_HW
implements CYGINT_HAL_ARM_AT91_SYS_INTERRUPT
+ implements CYGINT_DEVS_USB_AT91_HAS_USB
define_proc {
puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H
<pkgconf/hal_arm.h>"
@@ -82,8 +82,8 @@
display "AT91SAM7S variant used"
flavor data
default_value {"at91sam7s256"}
- legal_values {"at91sam7s32" "at91sam7s64" "at91sam7s128"
- "at91sam7s256"}
+ legal_values {"at91sam7s32" "at91sam7s321" "at91sam7s64"
+ "at91sam7s128" "at91sam7s256"}
description "
The AT91SAM7S microcontroller family has several variants,
the main differences being the amount of on-chip SRAM,
@@ -124,9 +124,9 @@
no_define
define -file system.h CYG_HAL_STARTUP
description "
- When targetting the AT91SAM7S eval board it is possible to build
+ When targeting the AT91SAM7S eval board it is possible to build
the system for either RAM bootstrap or ROM bootstrap(s). Select
- 'ram' when building programs to load into RAM using onboard
+ 'ram' when building programs to load into RAM using on board
debug software such as Angel or eCos GDB stubs. Select 'rom'
when building a stand-alone application which will be put
into ROM"
@@ -160,7 +160,7 @@
display "Divider for PLL clock"
flavor data
legal_values { 0 to 255 }
- default_value 14
+ default_value 24
description "
The X-tal clock is divided by this value when generating the
PLL clock"
@@ -170,7 +170,7 @@
display "Multiplier for PLL clock"
flavor data
legal_values { 0 to 2047 }
- default_value 145
+ default_value 125
description "
The X-tal clock is multiplied by this value when generating
the PLL clock."
@@ -181,20 +181,20 @@
flavor data
default_value { 32768 }
description "
- The slow clock is an LC oscilator which runs all the
+ The slow clock is an LC oscillator which runs all the
time. The accuracy of this clock is not very high and
- is temperature dependant"
+ is temperature dependent."
}
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
display "Number of communication channels on the board"
flavor data
- default_value 1
+ default_value 3
description "
- The AT91SAM7S development boards have only one USART serial
- port connector even though there are two real serial ports.
- Also don't confuse the debug port as a USART serial port. It
- needs a different driver."
+ The AT91SAM7S development boards has two Serial port connectors.
+ these correspond to USART0 and the Debug Serial port. The chip
+ has a third serial port which does not have a 9pin D
+ connector, but is accessible via the patch panel pins."
}
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
@@ -202,9 +202,9 @@
active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
flavor data
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
- default_value 0
+ default_value 2
description "
- The AT91SAM7S has two USART serial ports. This option
+ The AT91SAM7S has three serial ports. This option
chooses which port will be used to connect to a host
running GDB."
}
@@ -214,9 +214,9 @@
active_if
CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
flavor data
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
- default_value 0
+ default_value 2
description "
- The AT91SAM7S board has two USART serial ports. This option
+ The AT91SAM7S board has three USART serial ports. This option
chooses which port will be used for diagnostic output."
}
@@ -242,10 +242,10 @@
display "Dynamic calculation of baud rate"
default_value 0
description "
- The AT91SAM7S has a flexiable clock generation mechanism
+ The AT91SAM7S has a flexible clock generation mechanism
where the main clock used to drive peripherals can be
- changed during runtime. Such changes affect the serial port
- baud rate generaters. Enabling this option includes code
+ changed during run time. Such changes affect the serial port
+ baud rate generators. Enabling this option includes code
which calculates the baud rate setting dynamically from the
current clock settings. Without this option a static
calculation is performed which assumes the clock frequency
Index: hal/arm/at91/at91sam7s/current/include/plf_io.h
===================================================================
RCS file:
/cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/include/plf_io.h,v
retrieving revision 1.2
diff -u -r1.2 plf_io.h
--- hal/arm/at91/at91sam7s/current/include/plf_io.h 1 Mar 2006 20:43:18
-0000 1.2
+++ hal/arm/at91/at91sam7s/current/include/plf_io.h 13 Mar 2006 07:44:03
-0000
@@ -63,6 +63,12 @@
#define AT91_USART0 0xFFFC0000
#define AT91_USART1 0xFFFC4000
+// Define USART2 to be the debug UART. It is similar enough to a USART
+// that both the hal_diag and interrupt driven driver will work.
+// However trying to change parity, start/stop bits etc will not work.
+#define CYGNUM_HAL_INTERRUPT_USART2 CYGNUM_HAL_INTERRUPT_DBG
+#define AT91_USART2 AT91_DBG
+
#ifndef __ASSEMBLER__
#ifdef CYGBLD_HAL_ARM_AT91_BAUD_DYNAMIC
extern cyg_uint32 hal_at91_us_baud(cyg_uint32 baud);
Index: hal/arm/at91/at91sam7s/current/src/at91sam7s_misc.c
===================================================================
RCS file:
/cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/src/at91sam7s_misc.c,v
retrieving revision 1.2
diff -u -r1.2 at91sam7s_misc.c
--- hal/arm/at91/at91sam7s/current/src/at91sam7s_misc.c 1 Mar 2006 20:43:18
-0000 1.2
+++ hal/arm/at91/at91sam7s/current/src/at91sam7s_misc.c 13 Mar 2006 07:44:03
-0000
@@ -94,11 +94,12 @@
{
/* Enable the Serial devices to driver the serial port pins */
HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_PDR,
- AT91_PIO_PSR_RXD0 | AT91_PIO_PSR_TXD0);
+ AT91_PIO_PSR_RXD0 | AT91_PIO_PSR_TXD0 | AT91_PIO_PSR_DTXD);
/* Set the serial port pins to PIOA */
HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_ASR,
- AT91_PIO_PSR_RXD0 | AT91_PIO_PSR_TXD0);
+ AT91_PIO_PSR_RXD0 | AT91_PIO_PSR_TXD0 |
+ AT91_PIO_PSR_DRXD | AT91_PIO_PSR_DTXD);
#if !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
/* Enable the Serial devices to driver the serial port pins */
@@ -120,8 +121,7 @@
/* Enable peripheral clocks for USART 0 and 1 if they are to be used */
HAL_WRITE_UINT32(AT91_PMC+AT91_PMC_PCER,
AT91_PMC_PCER_US0 |
- AT91_PMC_PCER_US1 |
- CYGNUM_HAL_INTERRUPT_SYS);
+ AT91_PMC_PCER_US1);
#endif
#ifdef CYGBLD_HAL_ARM_AT91_TIMER_TC
Index: hal/arm/at91/var/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/ChangeLog,v
retrieving revision 1.31
diff -u -r1.31 ChangeLog
--- hal/arm/at91/var/current/ChangeLog 1 Mar 2006 18:13:03 -0000 1.31
+++ hal/arm/at91/var/current/ChangeLog 13 Mar 2006 07:44:04 -0000
@@ -1,3 +1,8 @@
+2006-03-10 Oliver Munz <[EMAIL PROTECTED]>
+
+ * src/hal_diag.c (cyg_hal_plf_serial_isr): Change the #ifdefs to
+ cleanly match the CDL.
+
2006-02-28 Andrew Lunn <[EMAIL PROTECTED]>
Oliver Munz <[EMAIL PROTECTED]>
Index: hal/arm/at91/var/current/src/hal_diag.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/src/hal_diag.c,v
retrieving revision 1.5
diff -u -r1.5 hal_diag.c
--- hal/arm/at91/var/current/src/hal_diag.c 12 Nov 2004 09:08:47 -0000
1.5
+++ hal/arm/at91/var/current/src/hal_diag.c 13 Mar 2006 07:44:05 -0000
@@ -269,12 +269,16 @@
return res;
}
-static channel_data_t at91_ser_channels[3] = {
+static channel_data_t
at91_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS] = {
+#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 0
{ (cyg_uint8*)AT91_USART0, 1000, CYGNUM_HAL_INTERRUPT_USART0,
CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
{ (cyg_uint8*)AT91_USART1, 1000, CYGNUM_HAL_INTERRUPT_USART1,
CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
-#ifdef AT91_USART2
+#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 2
{ (cyg_uint8*)AT91_USART2, 1000, CYGNUM_HAL_INTERRUPT_USART2,
CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD}
#endif
+#endif
+#endif
};
static void
@@ -286,16 +290,19 @@
cur =
CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
// Init channels
+#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 0
cyg_hal_plf_serial_init_channel(&at91_ser_channels[0]);
#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
cyg_hal_plf_serial_init_channel(&at91_ser_channels[1]);
-#endif
#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 2
cyg_hal_plf_serial_init_channel(&at91_ser_channels[2]);
#endif
+#endif
+#endif
// Setup procs in the vector table
// Set channel 0
+#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 0
CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &at91_ser_channels[0]);
@@ -319,7 +326,7 @@
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
-#endif
+
#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 2
CYGACC_CALL_IF_SET_CONSOLE_COMM(2);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
@@ -332,6 +339,8 @@
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
#endif
+#endif
+#endif
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
