? packages/devs/usb/at91 ? packages/hal/arm/at91/var/current/src/Kopie von timer_pit.c Index: packages/hal/arm/at91/at91sam7s/current/ChangeLog =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/ChangeLog,v retrieving revision 1.5 diff -u -r1.5 ChangeLog --- packages/hal/arm/at91/at91sam7s/current/ChangeLog 13 Mar 2006 07:48:20 -0000 1.5 +++ packages/hal/arm/at91/at91sam7s/current/ChangeLog 21 Mar 2006 22:33:40 -0000 @@ -1,3 +1,8 @@ +2006-03-21 Oliver Munz + + * hal_arm_at91sam7s.c: Add PIT-Initialisaton in the case if there is + no kernel (RedBoot as example). + 2006-03-10 Oliver Munz * hal_arm_at91sam7s.cdl: Change the PLL-defaults so that 96MHz is Index: packages/hal/arm/at91/at91sam7s/current/src/at91sam7s_misc.c =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/src/at91sam7s_misc.c,v retrieving revision 1.3 diff -u -r1.3 at91sam7s_misc.c --- packages/hal/arm/at91/at91sam7s/current/src/at91sam7s_misc.c 13 Mar 2006 07:48:20 -0000 1.3 +++ packages/hal/arm/at91/at91sam7s/current/src/at91sam7s_misc.c 21 Mar 2006 22:33:40 -0000 @@ -89,6 +89,9 @@ // ------------------------------------------------------------------------- // Hardware init +#ifdef CYGBLD_HAL_ARM_AT91_TIMER_PIT +extern cyg_uint32 _pit_period; +#endif void hal_plf_hardware_init (void) { @@ -131,6 +134,13 @@ AT91_PMC_PCER_TC2); #endif +#ifndef CYGVAR_KERNEL_COUNTERS_CLOCK /* Wenn der Kernel den sytem-timer nicht inizialisiert... */ +#ifdef CYGBLD_HAL_ARM_AT91_TIMER_PIT + _pit_period = 0xfffff; + HAL_WRITE_UINT32(AT91_PITC + AT91_PITC_PIMR, _pit_period | AT91_PITC_PIMR_PITEN); /* wird von hal_delay_us() gebraucht */ +#endif +#endif + #ifndef CYGPKG_IO_WATCHDOG /* Disable the watchdog. The eCos philosophy is that the watchdog is disabled unless the watchdog driver is used to enable it. Index: packages/hal/arm/at91/var/current/ChangeLog =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/ChangeLog,v retrieving revision 1.32 diff -u -r1.32 ChangeLog --- packages/hal/arm/at91/var/current/ChangeLog 13 Mar 2006 07:47:23 -0000 1.32 +++ packages/hal/arm/at91/var/current/ChangeLog 21 Mar 2006 22:33:41 -0000 @@ -1,3 +1,10 @@ +2006-03-21 Oliver Munz + + * src/timer_tc.c: compile only if CYGBLD_HAL_ARM_AT91_TIMER_PIT is + set + * src/timer_pit.c: better routines that work korrekt from 20us until + 4Gs or in other words <20us .. >130years - 32bit... + 2006-03-10 Oliver Munz * src/hal_diag.c (cyg_hal_plf_serial_isr): Change the #ifdefs to Index: packages/hal/arm/at91/var/current/src/timer_pit.c =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/src/timer_pit.c,v retrieving revision 1.1 diff -u -r1.1 timer_pit.c --- packages/hal/arm/at91/var/current/src/timer_pit.c 19 Feb 2006 19:08:28 -0000 1.1 +++ packages/hal/arm/at91/var/current/src/timer_pit.c 21 Mar 2006 22:33:41 -0000 @@ -48,6 +48,7 @@ //========================================================================*/ #include +#include #include // base types #include // assertion macros @@ -56,83 +57,66 @@ #include // ------------------------------------------------------------------------- // Use system clock -void -hal_clock_initialize(cyg_uint32 period) -{ - cyg_uint32 sr; - - CYG_ASSERT(CYGNUM_HAL_INTERRUPT_RTC == CYGNUM_HAL_INTERRUPT_PITC, - "Invalid timer interrupt"); - - /* Set Period Interval timer and enable interrupt */ - HAL_WRITE_UINT32((AT91_PITC + AT91_PITC_PIMR), - period | - AT91_PITC_PIMR_PITEN | - AT91_PITC_PIMR_PITIEN); - - // Read the status register to clear any pending interrupt - HAL_READ_UINT32(AT91_PITC + AT91_PITC_PISR, sr); + +#ifdef CYGBLD_HAL_ARM_AT91_TIMER_PIT + +cyg_uint32 _pit_period; + +void hal_clock_initialize(cyg_uint32 period){ + + // CYG_ASSERT(period > 500 && period < 10000, "Invalid clock period"); + + _pit_period = period; + + HAL_WRITE_UINT32(AT91_PITC + AT91_PITC_PIMR, _pit_period | AT91_PITC_PIMR_PITEN | AT91_PITC_PIMR_PITIEN); } -// This routine is called during a clock interrupt. -void -hal_clock_reset(cyg_uint32 vector, cyg_uint32 period) -{ - cyg_uint32 reg; - - /* Read the value register so that we clear the interrupt */ - HAL_READ_UINT32(AT91_PITC + AT91_PITC_PIVR, reg); +void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period){ + + cyg_uint32 sr; + + HAL_READ_UINT32(AT91_PITC + AT91_PITC_PIVR, sr); // Clear interrupt + + if (_pit_period != period) { + + hal_clock_initialize(period); + } } -// Read the current value of the clock, returning the number of hardware -// "ticks" that have occurred (i.e. how far away the current value is from -// the start) -void -hal_clock_read(cyg_uint32 *pvalue) -{ - cyg_uint32 ir; - - HAL_READ_UINT32(AT91_PITC + AT91_PITC_PIIR, ir); - *pvalue = ir & 0xfffff; +void hal_clock_read(cyg_uint32 *pvalue){ + + cyg_uint32 val; + + HAL_READ_UINT32(AT91_PITC + AT91_PITC_PIIR, val); + + *pvalue = val & 0xfffff; +// *pvalue = val & AT91_SYSC_CPIV; } -// ------------------------------------------------------------------------- -// -// Delay for some number of micro-seconds -// PIT is clocked at MCLK / 16 -// -void hal_delay_us(cyg_int32 usecs) -{ - cyg_int64 ticks; - cyg_uint32 val1, val2; - cyg_uint32 piv; - - // Calculate how many PIT ticks the required number of microseconds - // equate to. We do this calculation in 64 bit arithmetic to avoid - // overflow. - ticks = (((cyg_uint64)usecs) * - ((cyg_uint64)CYGNUM_HAL_ARM_AT91_CLOCK_SPEED))/16/1000000LL; - - // I've no idea why, but waiting for the number of ticks calculated - // above does not work by about a factor or 3. If anybody works out - // why, please let me know! - ticks = ticks / 3; - - HAL_READ_UINT32(AT91_PITC + AT91_PITC_PIMR, piv); - - while (ticks > 0) { - hal_clock_read(&val1); - do { - hal_clock_read(&val2); - } while (val1 == val2); - // Sometimes we miss a tick, maybe because of interrupt handling? - // So calculate the number of ticks, without making a big error - // with wrap around. - if (val2 > val1) - ticks -= (val2 - val1); - else - ticks--; - } + +void hal_delay_us(cyg_int32 usecs){ /* */ + + cyg_uint32 t_target; /* PITC-ticks to wait */ + cyg_uint32 t_old; /* start time */ + cyg_uint32 t_start; /* start time */ + cyg_uint32 t; /* now */ + cyg_uint32 overflows = 0; + + hal_clock_read(&t_start); + t_old = t_start; + + t_target = ((cyg_uint64) usecs * (cyg_uint64) CYGNUM_HAL_ARM_AT91_CLOCK_SPEED / 16) / 1000000; + + do { + hal_clock_read(&t); /* actual time */ + + if (t < t_old){ /* overrun occured? */ + overflows++; + } + t_old = t; + + } while (t - t_start + overflows * _pit_period < t_target); } +#endif // timer_pit.c Index: packages/hal/arm/at91/var/current/src/timer_tc.c =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/src/timer_tc.c,v retrieving revision 1.2 diff -u -r1.2 timer_tc.c --- packages/hal/arm/at91/var/current/src/timer_tc.c 25 Feb 2006 20:12:32 -0000 1.2 +++ packages/hal/arm/at91/var/current/src/timer_tc.c 21 Mar 2006 22:33:41 -0000 @@ -49,6 +49,7 @@ //========================================================================*/ #include +#include #include // base types #include // assertion macros @@ -60,6 +61,8 @@ // ------------------------------------------------------------------------- // Clock support +#ifdef CYGBLD_HAL_ARM_AT91_TIMER_TC + static cyg_uint32 _period; void hal_clock_initialize(cyg_uint32 period) @@ -157,4 +160,6 @@ } while ((stat & AT91_TC_SR_CPC) == 0); } +#endif + // timer_tc.c