diff -r -u5 -N -x CVS ecos_orig/packages/hal/arm/lpc2xxx/var/current/ChangeLog ecos_dev/packages/hal/arm/lpc2xxx/var/current/ChangeLog
--- ecos_orig/packages/hal/arm/lpc2xxx/var/current/ChangeLog    2006-05-08 15:55:44.078125000 +0100
+++ ecos_dev/packages/hal/arm/lpc2xxx/var/current/ChangeLog    2006-05-08 15:55:37.609375000 +0100
@@ -1,11 +1,16 @@
+2006-05-08  Andy Jackson <andy@grapevinetech.co.uk>
+
+    * src/lpc2xxx_misc.c: Fixed issue with VPBDIV initialisation
+    on non lpc22xx parts code.
+
 2006-05-08  Sergei Gavrikov  <sg@belvok.com>
 
     * src/lpc2xxx.misc (hal_hardware_init): Call HAL_PLF_HARDWARE_INIT
     for any platform specific initialization.
 
-2006-02-14  Andy Jackson <andy@grapevinetech.co.uk>
+2006-05-07  Andy Jackson <andy@grapevinetech.co.uk>
 
     * cdl/hal_arm_lpc2xxx.cdl: Added CYGHWR_HAL_ARM_LPC2XXX_FAMILY,
     CYGNUM_HAL_ARM_LPC2XXX_VPBDIV, CYGNUM_HAL_ARM_LPC2XXX_XCLKDIV
     and CYGHWR_HAL_ARM_LPC2XXX_IDLE_PWRSAVE. Changed 
     CYGHWR_HAL_ARM_LPC2XXX_EXTINT_ERRATA to a bool.
diff -r -u5 -N -x CVS ecos_orig/packages/hal/arm/lpc2xxx/var/current/src/lpc2xxx_misc.c ecos_dev/packages/hal/arm/lpc2xxx/var/current/src/lpc2xxx_misc.c
--- ecos_orig/packages/hal/arm/lpc2xxx/var/current/src/lpc2xxx_misc.c    2006-05-08 14:17:45.000000000 +0100
+++ ecos_dev/packages/hal/arm/lpc2xxx/var/current/src/lpc2xxx_misc.c    2006-05-08 16:01:08.609375000 +0100
@@ -199,13 +199,13 @@
     return (vpbdiv_reg);
 }
 
 // Set the VPBDIV register. The vpb bits are 1:0 and the xclk bits are 5:4. The
 // mapping of values passed to this routine to field values is:
-//			4 = divide by 4 (register bits 00)
-//			2 = divide by 2 (register bits 10)
-//			1 = divide by 1 (register bits 01)
+//        4 = divide by 4 (register bits 00)
+//        2 = divide by 2 (register bits 10)
+//        1 = divide by 1 (register bits 01)
 // This routine assumes that only these values can occur. As they are
 // generated in the CDL hopefully this should be the case. Fortunately
 // writing 11 merely causes the previous value to be retained.
 void lpc_set_vpbdiv(int vpbdiv, int xclkdiv)
 {
@@ -215,27 +215,36 @@
     // Update VPBDIV register
 #ifdef CYGHWR_HAL_ARM_LPC2XXX_FAMILY_LPC22XX
     HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE +
                      CYGARC_HAL_LPC2XXX_REG_VPBDIV,
                      ((xclkdiv & 0x3) << 4) | (vpbdiv & 0x3));
+    lpc_xclk = lpc_cclk / xclkdiv;
 #else
     HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE + 
                      CYGARC_HAL_LPC2XXX_REG_VPBDIV, vpbdiv & 0x3);
+    lpc_xclk = 0;        // Obvious bad value
 #endif
     
     lpc_pclk = lpc_cclk / vpbdiv;
-    lpc_xclk = lpc_cclk / xclkdiv;
 }
 
-// Perform variant setup
+// Perform variant setup. To utilise platform specific
+// initialisation, add the following to the plf_io.h file:
+//        #ifndef __ASSEMBLER__
+//        extern void hal_plf_hardware_init(void);
+//        #define HAL_PLF_HARDWARE_INIT() hal_plf_hardware_init()
+//        #endif
+// The necessary code goes in the platform XXX_misc.c file.
 void hal_hardware_init(void)
 {
     lpc_cclk = CYGNUM_HAL_ARM_LPC2XXX_CLOCK_SPEED;
 
 #ifdef CYGHWR_HAL_ARM_LPC2XXX_FAMILY_LPC22XX
     lpc_set_vpbdiv(CYGNUM_HAL_ARM_LPC2XXX_VPBDIV,
                    CYGNUM_HAL_ARM_LPC2XXX_XCLKDIV);
+#else
+    lpc_set_vpbdiv(CYGNUM_HAL_ARM_LPC2XXX_VPBDIV, 1);
 #endif
 
 #ifdef HAL_PLF_HARDWARE_INIT
     // Perform any platform specific initializations
     HAL_PLF_HARDWARE_INIT();
@@ -310,11 +319,11 @@
         // Clear the external interrupt
         HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_SCB_BASE + 
                          CYGARC_HAL_LPC2XXX_REG_EXTINT, vector);
       }
     
-    //
+    // Acknowledge interrupt in the VIC
     HAL_WRITE_UINT32(CYGARC_HAL_LPC2XXX_REG_VIC_BASE + 
                      CYGARC_HAL_LPC2XXX_REG_VICVECTADDR, 0);  
 }
 
 // This provides control over how an interrupt signal is detected.