Index: packages/hal/arm/at91/at91sam7s/current/ChangeLog =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/ChangeLog,v retrieving revision 1.10 diff -u -r1.10 ChangeLog --- packages/hal/arm/at91/at91sam7s/current/ChangeLog 7 Jan 2007 15:22:52 -0000 1.10 +++ packages/hal/arm/at91/at91sam7s/current/ChangeLog 17 Jan 2007 14:25:42 -0000 @@ -1,3 +1,8 @@ +2007-01-17 John Eigelaar + * include/plf_io.h + * src/at91sam7s_misc.c + Added code to initialise the platform ethernet hardware if need be + 2007-01-02 Uwe Kindler * cdl/hal_arm_at91sam7s.cdl Moved HAL_PLATFORM_XXX defines and Index: packages/hal/arm/at91/at91sam7s/current/include/plf_io.h =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/include/plf_io.h,v retrieving revision 1.6 diff -u -r1.6 plf_io.h --- packages/hal/arm/at91/at91sam7s/current/include/plf_io.h 9 Sep 2006 13:26:05 -0000 1.6 +++ packages/hal/arm/at91/at91sam7s/current/include/plf_io.h 11 Jan 2007 14:24:35 -0000 @@ -62,6 +62,9 @@ #define AT91_SPI AT91_SPI0 +//Extra SPI control bits +#define AT91_SPI_MR_MODFDIS (1<<4) + // DMA registers #define AT91_SPI_RPR 0x100 // Receive Pointer Register #define AT91_SPI_RCR 0x104 // Receive Counter Register @@ -188,8 +191,14 @@ extern void hal_plf_hardware_init(void); #define HAL_PLF_HARDWARE_INIT() \ hal_plf_hardware_init() + +#ifdef CYGHWR_HAL_ARM_AT91SAM7X +extern void hal_plf_eth_init(void); +#define HAL_PLF_ETH_INIT() \ + hal_plf_eth_init() #endif +#endif //__ASSEMBLER__ #endif //CYGONCE_HAL_PLF_IO_H Index: packages/hal/arm/at91/at91sam7s/current/src/at91sam7s_misc.c =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/src/at91sam7s_misc.c,v retrieving revision 1.4 diff -u -r1.4 at91sam7s_misc.c --- packages/hal/arm/at91/at91sam7s/current/src/at91sam7s_misc.c 2 Jun 2006 18:15:29 -0000 1.4 +++ packages/hal/arm/at91/at91sam7s/current/src/at91sam7s_misc.c 11 Jan 2007 14:24:35 -0000 @@ -120,6 +120,17 @@ watchdog driver, hence the conditional compilation. */ HAL_WRITE_UINT32(AT91_WDTC + AT91_WDTC_WDMR, AT91_WDTC_WDMR_DIS); #endif + +/* Perform some platform specific bits to get the Ethernet + hardware setup specifically if a specific phy is used and does not + start in the correct mode a function needs to be supplied as part of + the plf to do the necessary +*/ +#ifdef CYGPKG_DEVS_ETH_ARM_AT91 +#ifdef HAL_PLF_ETH_INIT + HAL_PLF_ETH_INIT(); +#endif +#endif } // Calculate the baud value to be programmed into the serial port baud Index: packages/hal/arm/at91/at91sam7xek/current/ChangeLog =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7xek/current/ChangeLog,v retrieving revision 1.2 diff -u -r1.2 ChangeLog --- packages/hal/arm/at91/at91sam7xek/current/ChangeLog 7 Jan 2007 15:23:26 -0000 1.2 +++ packages/hal/arm/at91/at91sam7xek/current/ChangeLog 17 Jan 2007 14:28:54 -0000 @@ -1,3 +1,7 @@ +2007-01-17 John Eigelaar + * Added hal_plf_eth_init() in order to initialise the + Davicom 9161A PHY properly on the Evaluation board + 2007-01-02 Uwe Kindler * cdl/hal_arm_at91sam7s.cdl Moved HAL_PLATFORM_XXX defines and Index: packages/hal/arm/at91/at91sam7xek/current/src/at91sam7xek_misc.c =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7xek/current/src/at91sam7xek_misc.c,v retrieving revision 1.1 diff -u -r1.1 at91sam7xek_misc.c --- packages/hal/arm/at91/at91sam7xek/current/src/at91sam7xek_misc.c 2 Jun 2006 18:22:47 -0000 1.1 +++ packages/hal/arm/at91/at91sam7xek/current/src/at91sam7xek_misc.c 17 Jan 2007 14:30:55 -0000 @@ -73,5 +73,40 @@ HAL_ARM_AT91_GPIO_PUT(AT91_GPIO_PB22, !(val & 8)); } +void hal_plf_eth_init(void) +{ + cyg_uint32 stat; + /* Enable the PIOB Clock */ + HAL_WRITE_UINT32(AT91_PMC + AT91_PMC_PCER, AT91_PMC_PCER_PIOB); + + /* RXDV / Testmode select */ + HAL_ARM_AT91_GPIO_CFG_DIRECTION(AT91_GPIO_PB15, AT91_PIN_IN); + HAL_ARM_AT91_GPIO_CFG_DIRECTION(AT91_GPIO_PB15, AT91_PIN_PULLUP_DISABLE); + + //TODO: The errata reports that the RMII mode for the SAM7X does not work. + // It would probably still be a good idea to use the RMII/MII CDL + // configuration to select the appropriate mode here + /* COL / !MII select */ + HAL_ARM_AT91_GPIO_CFG_DIRECTION(AT91_GPIO_PB16, AT91_PIN_IN); + HAL_ARM_AT91_GPIO_CFG_DIRECTION(AT91_GPIO_PB16, AT91_PIN_PULLUP_DISABLE); + + /* TXCLK / ISOLATE */ + HAL_ARM_AT91_GPIO_CFG_DIRECTION(AT91_GPIO_PB0, AT91_PIN_IN); + HAL_ARM_AT91_GPIO_CFG_DIRECTION(AT91_GPIO_PB0, AT91_PIN_PULLUP_DISABLE); + + /* Power Down Mode */ + HAL_ARM_AT91_GPIO_CFG_DIRECTION(AT91_GPIO_PB18, AT91_PIN_OUT); + HAL_ARM_AT91_GPIO_PUT(AT91_GPIO_PB19,0); + + /* All the lines setup correctly now do a external reset as let the phy + start up in the correct mode */ + HAL_WRITE_UINT32(AT91_RST+AT91_RST_RMR,AT91_RST_RMR_KEY|(1<<0x8)); + HAL_WRITE_UINT32(AT91_RST+AT91_RST_RCR,AT91_RST_RCR_KEY|AT91_RST_RCR_EXTRST); + do + { + HAL_READ_UINT32(AT91_RST+AT91_RST_RSR,stat); + }while(!(stat&AT91_RST_RSR_NRST_SET)); +} + //-------------------------------------------------------------------------- // EOF at91sam7sek_misc.c Index: packages/hal/arm/at91/var/current/ChangeLog =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/ChangeLog,v retrieving revision 1.38 diff -u -r1.38 ChangeLog --- packages/hal/arm/at91/var/current/ChangeLog 9 Sep 2006 13:26:22 -0000 1.38 +++ packages/hal/arm/at91/var/current/ChangeLog 17 Jan 2007 14:34:46 -0000 @@ -1,3 +1,8 @@ +2007-01-17 John Eigelaar + + * include/var_io.h: Fixed up the EMAC definitions to work + with the brand new EMAC driver + 2006-09-08 John Eigelaar * include/var_io.h: Added definition for SPI MODFDIS bit Index: packages/hal/arm/at91/var/current/include/var_io.h =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/include/var_io.h,v retrieving revision 1.18 diff -u -r1.18 var_io.h --- packages/hal/arm/at91/var/current/include/var_io.h 9 Sep 2006 13:26:22 -0000 1.18 +++ packages/hal/arm/at91/var/current/include/var_io.h 12 Jan 2007 07:14:06 -0000 @@ -1849,45 +1849,45 @@ #endif -#define AT91_EMAC_CTL (0x00) // Network Control -#define AT91_EMAC_CTL_LB (1 << 0) // Loopback -#define AT91_EMAC_CTL_LBL (1 << 1) // Loopback Local -#define AT91_EMAC_CTL_RE (1 << 2) // Receiver Enable -#define AT91_EMAC_CTL_TX (1 << 3) // Transmit Enable -#define AT91_EMAC_CTL_MPE (1 << 4) // Management Port Enable -#define AT91_EMAC_CTL_CSR (1 << 5) // Clear Statistics Registers -#define AT91_EMAC_CTL_ISR (1 << 6) // Increment Statistics Registers -#define AT91_EMAC_CTL_WES (1 << 7) // Write Enable for Statistics Registers -#define AT91_EMAC_CTL_BP (1 << 8) // Back Pressure -#define AT91_EMAC_CTL_TSTART (1 << 9) // Start Transmitter -#define AT91_EMAC_CTL_THALT (1 << 10) // Halt Transmitter - -#define AT91_EMAC_CFG (0x04) // Network Configuration -#define AT91_EMAC_CFG_SPD_10Mbps (0 << 0) // 10Mbps line speed -#define AT91_EMAC_CFG_SPD_100Mbps (1 << 0) // 100Mbps line speed -#define AT91_EMAC_CFG_FD (1 << 1) // Full Deplex -#define AT91_EMAC_CFG_BR (1 << 2) // Bit Rate -#define AT91_EMAC_CFG_CAF (1 << 4) // Copy All Frames -#define AT91_EMAC_CFG_NBC (1 << 5) // Don't receiver Broadcasts -#define AT91_EMAC_CFG_MTI (1 << 6) // Multicast Hash Enable -#define AT91_EMAC_CFG_UNI (1 << 7) // Unicast hash enable -#define AT91_EMAC_CFG_BIG (1 << 8) // Receive upto 1522 byte frames -#define AT91_EMAC_CFG_EAE (1 << 9) // External Address match Enable -#define AT91_EMAC_CFG_CLK_HCLK_8 (0 << 10) // HCLK divided by 8 -#define AT91_EMAC_CFG_CLK_HCLK_16 (1 << 10) // HCLK divided by 16 -#define AT91_EMAC_CFG_CLK_HCLK_32 (2 << 10) // HCLK divided by 32 -#define AT91_EMAC_CFG_CLK_HCLK_64 (3 << 10) // HCLK divided by 64 -#define AT91_EMAC_CFG_CLK_MASK (3 << 10) // HCLK mask -#define AT91_EMAC_CFG_CLK_RTY (1 << 12) // Retry Test -#define AT91_EMAC_CFG_CLK_RMII (1 << 13) // Enable RMII mode -#define AT91_EMAC_CFG_CLK_MII (0 << 13) // Enable MII mode -#define AT91_EMAC_SR (0x08) // Network Status -#define AT91_EMAC_SR_MDIO_MASK (1 << 1) // MDIO Pin status -#define AT91_EMAC_SR_IDLE (1 << 2) // PHY logical is idle -#define AT91_EMAC_TAR (0x0c) // Transmit Address -#define AT91_EMAC_TCR (0x10) // Transmit Control -#define AT91_EMAC_TCR_LEN_MASK (0x3ff << 0) // Transmit frame length -#define AT91_EMAC_TCR_NCRC ( 1 << 15) // No CRC added by MAC +#define AT91_EMAC_NCR (0x00) // Network Control +#define AT91_EMAC_NCR_LB (1 << 0) // Loopback +#define AT91_EMAC_NCR_LBL (1 << 1) // Loopback Local +#define AT91_EMAC_NCR_RE (1 << 2) // Receiver Enable +#define AT91_EMAC_NCR_TX (1 << 3) // Transmit Enable +#define AT91_EMAC_NCR_MPE (1 << 4) // Management Port Enable +#define AT91_EMAC_NCR_CSR (1 << 5) // Clear Statistics Registers +#define AT91_EMAC_NCR_ISR (1 << 6) // Increment Statistics Registers +#define AT91_EMAC_NCR_WES (1 << 7) // Write Enable for Statistics Registers +#define AT91_EMAC_NCR_BP (1 << 8) // Back Pressure +#define AT91_EMAC_NCR_TSTART (1 << 9) // Start Transmitter +#define AT91_EMAC_NCR_THALT (1 << 10) // Halt Transmitter + +#define AT91_EMAC_NCFG (0x04) // Network Configuration +#define AT91_EMAC_NCFG_SPD_10Mbps (0 << 0) // 10Mbps line speed +#define AT91_EMAC_NCFG_SPD_100Mbps (1 << 0) // 100Mbps line speed +#define AT91_EMAC_NCFG_FD (1 << 1) // Full Deplex +#define AT91_EMAC_NCFG_BR (1 << 2) // Bit Rate +#define AT91_EMAC_NCFG_CAF (1 << 4) // Copy All Frames +#define AT91_EMAC_NCFG_NBC (1 << 5) // Don't receiver Broadcasts +#define AT91_EMAC_NCFG_MTI (1 << 6) // Multicast Hash Enable +#define AT91_EMAC_NCFG_UNI (1 << 7) // Unicast hash enable +#define AT91_EMAC_NCFG_BIG (1 << 8) // Receive upto 1522 byte frames +#define AT91_EMAC_NCFG_EAE (1 << 9) // External Address match Enable +#define AT91_EMAC_NCFG_CLK_HCLK_8 (0 << 10) // HCLK divided by 8 +#define AT91_EMAC_NCFG_CLK_HCLK_16 (1 << 10) // HCLK divided by 16 +#define AT91_EMAC_NCFG_CLK_HCLK_32 (2 << 10) // HCLK divided by 32 +#define AT91_EMAC_NCFG_CLK_HCLK_64 (3 << 10) // HCLK divided by 64 +#define AT91_EMAC_NCFG_CLK_MASK (3 << 10) // HCLK mask +#define AT91_EMAC_NCFG_CLK_RTY (1 << 12) // Retry Test +#define AT91_EMAC_NCFG_CLK_RMII (1 << 13) // Enable RMII mode +#define AT91_EMAC_NCFG_CLK_MII (0 << 13) // Enable MII mode +#define AT91_EMAC_NCFG_RLCE (0 << 16) // Receive Length Check Enable + + +#define AT91_EMAC_NSR (0x08) // Network Status +#define AT91_EMAC_NSR_MDIO_MASK (1 << 1) // MDIO Pin status +#define AT91_EMAC_NSR_IDLE (1 << 2) // PHY logical is idle + #define AT91_EMAC_TSR (0x14) // Transmit Status #define AT91_EMAC_TSR_OVR (1 << 0) // Overrun #define AT91_EMAC_TSR_COL (1 << 1) // Collision occurred @@ -1896,12 +1896,15 @@ #define AT91_EMAC_TSR_BNQ (1 << 4) // Buffer Not Queues #define AT91_EMAC_TSR_COMP (1 << 5) // Transmission Complete #define AT91_EMAC_TSR_UND (1 << 6) // Transmit Underrun + #define AT91_EMAC_RBQP (0x18) // Receiver Buffer Queue Pointer #define AT91_EMAC_TBQP (0x1c) // Transmit Buffer Queue Pointer + #define AT91_EMAC_RSR (0x20) // Receiver Status #define AT91_EMAC_RSR_BNA (1 << 0) // Buffer Not Available #define AT91_EMAC_RSR_REC (1 << 1) // Frame Received #define AT91_EMAC_RSR_OVR (1 << 2) // Transmit Buffer Overrun + #define AT91_EMAC_ISR (0x24) // Interrupt Status #define AT91_EMAC_ISR_DONE (1 << 0) // Management Done #define AT91_EMAC_ISR_RCOM (1 << 1) // Receiver Complete @@ -1918,35 +1921,46 @@ #define AT91_EMAC_IER (0x28) // Interrupt Enable #define AT91_EMAC_IDR (0x2c) // Interrupt Disable #define AT91_EMAC_IMR (0x30) // Interrupt Mask + #define AT91_EMAC_MAN (0x34) // PHY Maintenance -#define AT91_EMAC_MAN_DATA_MASK (0xffff << 0) // Data to/from PHY -#define AT91_EMAC_MAN_CODE (2 << 16) // Code -#define AT91_EMAC_MAN_REGA_MASK (0x1f << 18) // Register Address Mask +#define AT91_EMAC_MAN_DATA_MASK (0xffff<<0) // Data to/from PHY +#define AT91_EMAC_MAN_CODE (2<<16) // Code +#define AT91_EMAC_MAN_REGA_MASK (0x1f<<18) // Register Address Mask #define AT91_EMAC_MAN_REGA_SHIFT (18) // Register Address Shift -#define AT91_EMAC_MAN_PHY_MASK (0x1f << 23) // PHY Address Mask +#define AT91_EMAC_MAN_PHY_MASK (0x1f<<23) // PHY Address Mask #define AT91_EMAC_MAN_PHY_SHIFT (23) // PHY Address Shift -#define AT91_EMAC_MAN_RD (2 << 28) // Read operation -#define AT91_EMAC_MAN_WR (1 << 28) // Write Operation -#define AT91_EMAC_MAN_HIGH (1 << 30) // Must be set to 1 -#define AT91_EMAC_FRA (0x40) // Frames Transmitted OK -#define AT91_EMAC_SCOL (0x44) // Single Collision Frame -#define AT91_EMAC_MCOL (0x48) // Multiple Collision Frame -#define AT91_EMAC_OK (0x4c) // Frames Received OK -#define AT91_EMAC_SEQE (0x50) // Frame Check Sequence Error +#define AT91_EMAC_MAN_RD (2<<28) // Read operation +#define AT91_EMAC_MAN_WR (1<<28) // Write Operation +#define AT91_EMAC_MAN_SOF (1<<30) // Must be set to 01 +#define AT91_EMAC_MAN_PHYA(x) ((x&0x1f)<<23) // Create a PHY Address +#define AT91_EMAC_MAN_REGA(x) ((x&0x1f)<<18) // Create a Register Address +#define AT91_EMAC_MAN_DATA(x) (x&0xffff) // Create a Data word + + +#define AT91_EMAC_PTR (0x38) // Pause Time Register +#define AT91_EMAC_PFR (0x3C) // Pause Frames Received +#define AT91_EMAC_FTO (0x40) // Frames Transmitted OK +#define AT91_EMAC_SCF (0x44) // Single Collision Frame +#define AT91_EMAC_MCF (0x48) // Multiple Collision Frame +#define AT91_EMAC_FRO (0x4c) // Frames Received OK +#define AT91_EMAC_FCSE (0x50) // Frame Check Sequence Error #define AT91_EMAC_ALE (0x54) // Alignment Error #define AT91_EMAC_DTR (0x58) // Deferred Transmission Frame #define AT91_EMAC_LCOL (0x5c) // Late Collision -#define AT91_EMAC_XCOL (0x60) // Excessive Collisions - ECAL!! -#define AT91_EMAC_CSE (0x64) // Carrier Sense Error -#define AT91_EMAC_TUE (0x68) // Transmit Underrun Error -#define AT91_EMAC_CDE (0x6c) // Code Error -#define AT91_EMAC_ELR (0x70) // Excessive Length -#define AT91_EMAC_RJB (0x74) // Receiver Jabber -#define AT91_EMAC_USF (0x78) // Undersize Frame -#define AT91_EMAC_SQEE (0x7c) // SEQ Test Error -#define AT91_EMAC_DRFC (0x80) // Discarded RX Frame -#define AT91_EMAC_HSH (0x90) // Hash Address High [63:21] -#define AT91_EMAC_HSL (0x94) // Hash Address Low [31:0] +#define AT91_EMAC_XCOL (0x60) // Excessive Collisions - ECOL!! +#define AT91_EMAC_TUND (0x64) // Transmit Underrun Error +#define AT91_EMAC_CSE (0x68) // Carrier Sense Error +#define AT91_EMAC_RRE (0x6c) // Receive Resource Errors +#define AT91_EMAC_ROV (0x70) // Receive Overrun +#define AT91_EMAC_RSE (0x74) // Receiver Symbol erros +#define AT91_EMAC_ELE (0x78) // Excessive Length Errors +#define AT91_EMAC_RJE (0x7c) // Receive Jabber Errors +#define AT91_EMAC_USF (0x80) // Undersize Frame Errors +#define AT91_EMAC_STE (0x84) // SQE Test Errors +#define AT91_EMAC_RLE (0x88) // Receive Length Field Mismatch + +#define AT91_EMAC_HRB (0x90) // Hash Address Low [31:0] +#define AT91_EMAC_HRT (0x94) // Hash Address High [63:32] #define AT91_EMAC_SA1L (0x98) // Specific Address 1 Low, First 4 bytes #define AT91_EMAC_SA1H (0x9c) // Specific Address 1 High, Last 2 bytes #define AT91_EMAC_SA2L (0xa0) // Specific Address 2 Low, First 4 bytes @@ -1955,9 +1969,15 @@ #define AT91_EMAC_SA3H (0xac) // Specific Address 3 High, Last 2 bytes #define AT91_EMAC_SA4L (0xb0) // Specific Address 4 Low, First 4 bytes #define AT91_EMAC_SA4H (0xb4) // Specific Address 4 High, Last 2 bytes +#define AT91_EMAC_TID (0xb8) // Type ID Checking Register + // +#define AT91_EMAC_USRIO (0xc0) // User IO Register +#define AT91_EMAC_USRIO_RMII (1<<0) // RMII Mode +#define AT91_EMAC_USRIO_CLKEN (1<<1) // Clock Enable // Receiver Buffer Descriptor #define AT91_EMAC_RBD_ADDR 0x0 // Address to beginning of buffer +#define AT91_EMAC_RBD_ADDR_MASK (0xFFFFFFFC) // Address Mask masking the reserved bits #define AT91_EMAC_RBD_ADDR_OWNER_EMAC (0 << 0) // EMAC owns receiver buffer #define AT91_EMAC_RBD_ADDR_OWNER_SW (1 << 0) // SW owns receiver buffer #define AT91_EMAC_RBD_ADDR_WRAP (1 << 1) // Last receiver buffer