-----Original Message-----
From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] On Behalf Of Andrew Lunn
Sent: Thursday, February 15, 2007 1:23 AM
To: John Eigelaar
Cc: [email protected]
Subject: Re: AT91 EMAC
Hi John
Could you explain the background to doing a reset at the end of
hal_plf_eth_init(). I would like to understand this a bit more. It
seems to be causing my JTAG debugger a problem.
Thanks
Andrew
Hi Andrew,
The Davicom DM9161A PHY has several pins (POWERDOWN, TESTMODE, ISOLATE,
RMII/MII etc.) that are multiplexed to latch a value on power-on or hard
reset.
The default AT91 GPIO state is configured as inputs with pull-ups enabled.
This causes the PHY to start up in Powered down, Isolate and Testmode. The
get around this the pins are setup to the proper required state and a hard
reset is done on the PHY for the right values to be latched.
This is by far the easiest way of achieving the desired PHY configuration.
A more elegant solution would be to put the PHY in the proper mode via the
serial management interface. However I have never tried this and I am not
sure whether the Serial Management Interface is operational during test mode
and whether a soft reset will clear test mode with the pins set in the
proper way.
Well that's about it...
John
