On Fri, Aug 17, 2007 at 04:02:09PM +0200, Hans Rosenfeld wrote:
> A less simple solution would be to fix the drivers and the kintr0 test
> to use configurable priorities. If it wouldn't involve kintr0 I would
> just do that.
I decided to do that now, but ignored kintr0 for now.
Attached are patches to the CAN, I2C, SPI, serial and the NS DP83902A
drivers to add options to change the interrupt priorities, and a patch
to the LPC2xxx HAL to add a VIC component which works as parent for
these options.
The changes to the generic serial and the NS DP83902A drivers are
minimal, other code using those drivers should not be affected.
--
%SYSTEM-F-ANARCHISM, The operating system has been overthrown
Index: ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/can/arm/lpc2xxx/current/ChangeLog,v
retrieving revision 1.5
diff -u -r1.5 ChangeLog
--- ChangeLog 17 Aug 2007 08:48:57 -0000 1.5
+++ ChangeLog 17 Aug 2007 15:25:04 -0000
@@ -1,3 +1,8 @@
+2007-08-17 Hans Rosenfeld <[EMAIL PROTECTED]>
+
+ * cdl/can_lpc2xxx.cdl, src/can_lpc2xxx.src: add options to set the
+ interrupt priorities
+
2007-08-17 Hans Rosenfeld <[EMAIL PROTECTED]>
* src/can_lpc2xxx.c: The definition of "info" is missing when only
Index: cdl/can_lpc2xxx.cdl
===================================================================
RCS file:
/cvs/ecos/ecos/packages/devs/can/arm/lpc2xxx/current/cdl/can_lpc2xxx.cdl,v
retrieving revision 1.2
diff -u -r1.2 can_lpc2xxx.cdl
--- cdl/can_lpc2xxx.cdl 31 Jul 2007 07:53:36 -0000 1.2
+++ cdl/can_lpc2xxx.cdl 17 Aug 2007 15:25:04 -0000
@@ -143,7 +143,19 @@
Check this box to turn ON debug options for LPC2XXXX
CAN device driver."
}
-
+
+ cdl_option CYGNUM_DEVS_CAN_LPC2XXX_PRIO {
+ display "Interrupt priority for CAN and Acceptance Filter"
+ parent CYGHWR_HAL_ARM_LPC2XXX_VIC
+ active_if CYGHWR_HAL_ARM_LPC2XXX_VIC
+ flavor data
+ default_value 7
+ legal_values 0 to 16
+ description "The interrupt priority corresponds to the vector
+ number in the Vectored Interrupt Controller. Lower
+ numbers designate higher priorities."
+ }
+
# Support up to 4 on-chip CAN modules. The number may vary between
# processor variants so it is easy to update this here
for { set ::channel 0 } { $::channel < 4 } { incr ::channel } {
@@ -229,6 +241,32 @@
identifier."
}
+ cdl_option CYGNUM_DEVS_CAN_LPC2XXX_CAN[set ::channel]_TX_PRIO {
+ display "TX interrupt priority for CAN module [set
::channel]"
+ parent CYGHWR_HAL_ARM_LPC2XXX_VIC
+ active_if CYGHWR_HAL_ARM_LPC2XXX_VIC
+ active_if CYGINT_DEVS_CAN_LPC2XXX_CAN[set ::channel]
+ flavor data
+ default_value [set ::channel] * 2 + 8
+ legal_values 0 to 16
+ description "The interrupt priority corresponds to the vector
+ number in the Vectored Interrupt Controller.
Lower
+ numbers designate higher priorities."
+ }
+
+ cdl_option CYGNUM_DEVS_CAN_LPC2XXX_CAN[set ::channel]_RX_PRIO {
+ display "RX interrupt priority for CAN module [set
::channel]"
+ parent CYGHWR_HAL_ARM_LPC2XXX_VIC
+ active_if CYGHWR_HAL_ARM_LPC2XXX_VIC
+ active_if CYGINT_DEVS_CAN_LPC2XXX_CAN[set ::channel]
+ flavor data
+ default_value [set ::channel] * 2 + 9
+ legal_values 0 to 16
+ description "The interrupt priority corresponds to the vector
+ number in the Vectored Interrupt Controller.
Lower
+ numbers designate higher priorities."
+ }
+
}
}
Index: src/can_lpc2xxx.c
===================================================================
RCS file:
/cvs/ecos/ecos/packages/devs/can/arm/lpc2xxx/current/src/can_lpc2xxx.c,v
retrieving revision 1.4
diff -u -r1.4 can_lpc2xxx.c
--- src/can_lpc2xxx.c 17 Aug 2007 08:48:57 -0000 1.4
+++ src/can_lpc2xxx.c 17 Aug 2007 15:25:05 -0000
@@ -348,11 +348,15 @@
#if CYGINT_IO_CAN_CHANNELS == 1
#define CAN_CTRL_BASE(_extra_) CAN_CTRL_SINGLETON_BASE
#define CAN_ISRVEC(_extra_) CAN_SINGLETON_ISRVEC
+#define CAN_TXPRIO(_extra_) CAN_SINGLETON_TXPRIO
+#define CAN_RXPRIO(_extra_) CAN_SINGLETON_RXPRIO
#define CAN_DECLARE_INFO(_chan_)
#define CAN_DECLARE_CHAN(_data_)
#else
#define CAN_CTRL_BASE(_extra_) ((_extra_)->base)
#define CAN_ISRVEC(_extra_) ((_extra_)->isrvec)
+#define CAN_TXPRIO(_extra_) ((_extra_)->txprio)
+#define CAN_RXPRIO(_extra_) ((_extra_)->rxprio)
#define CAN_DECLARE_INFO(_chan_) lpc2xxx_can_info_t *info =
(lpc2xxx_can_info_t *)chan->dev_priv;
#define CAN_DECLARE_CHAN(_data_) can_channel *chan = (can_channel *)data;
#endif // CYGINT_IO_CAN_CHANNELS == 1
@@ -425,6 +429,8 @@
#if CYGINT_IO_CAN_CHANNELS > 1
cyg_uint32 base; // Per-bus h/w details
cyg_uint8 isrvec; // ISR vector (peripheral id)
+ cyg_uint8 txprio; // TX ISR priority
+ cyg_uint8 rxprio; // RX ISR priority
#endif
} lpc2xxx_can_info_t;
@@ -438,11 +444,13 @@
//
#define LPC2XXX_CTRL_NOT_INITIALIZED 0xFF
#if CYGINT_IO_CAN_CHANNELS > 1
-#define LPC2XXX_CAN_INFO(_l, _base, _isrvec, _flags)
\
+#define LPC2XXX_CAN_INFO(_l, _base, _isrvec, _txprio, _rxprio, _flags)
\
lpc2xxx_can_info_t _l = {
\
state : LPC2XXX_CTRL_NOT_INITIALIZED,
\
base : (_base),
\
isrvec : (_isrvec),
\
+ txprio : (_txprio),
\
+ rxprio : (_rxprio),
\
flags : (_flags),
\
icr : 0,
\
LPC2XXX_CAN_INFO_LAST_TX_ID_INIT
\
@@ -517,6 +525,8 @@
LPC2XXX_CAN_INFO(lpc2xxx_can0_info,
CAN_CTRL_1_REG_BASE,
CYGNUM_HAL_INTERRUPT_CAN1_TX,
+ CYGNUM_DEVS_CAN_LPC2XXX_CAN0_TX_PRIO,
+ CYGNUM_DEVS_CAN_LPC2XXX_CAN0_RX_PRIO,
CAN0_FLAG_STARTUP_ACCFILT_SETUP);
#endif
@@ -524,6 +534,8 @@
LPC2XXX_CAN_INFO(lpc2xxx_can1_info,
CAN_CTRL_2_REG_BASE,
CYGNUM_HAL_INTERRUPT_CAN2_TX,
+ CYGNUM_DEVS_CAN_LPC2XXX_CAN1_TX_PRIO,
+ CYGNUM_DEVS_CAN_LPC2XXX_CAN1_RX_PRIO,
CAN1_FLAG_STARTUP_ACCFILT_SETUP);
#endif
@@ -531,6 +543,8 @@
LPC2XXX_CAN_INFO(lpc2xxx_can2_info,
CAN_CTRL_3_REG_BASE,
CYGNUM_HAL_INTERRUPT_CAN3_TX,
+ CYGNUM_DEVS_CAN_LPC2XXX_CAN2_TX_PRIO,
+ CYGNUM_DEVS_CAN_LPC2XXX_CAN2_RX_PRIO,
CAN2_FLAG_STARTUP_ACCFILT_SETUP);
#endif
@@ -538,6 +552,8 @@
LPC2XXX_CAN_INFO(lpc2xxx_can3_info,
CAN_CTRL_4_REG_BASE,
CYGNUM_HAL_INTERRUPT_CAN4_TX,
+ CYGNUM_DEVS_CAN_LPC2XXX_CAN3_TX_PRIO,
+ CYGNUM_DEVS_CAN_LPC2XXX_CAN3_RX_PRIO,
CAN3_FLAG_STARTUP_ACCFILT_SETUP);
#endif
#else // CYGINT_IO_CAN_CHANNELS == 1
@@ -545,24 +561,32 @@
LPC2XXX_CAN_INFO(lpc2xxx_can0_info, CAN0_FLAG_STARTUP_ACCFILT_SETUP);
#define CAN_CTRL_SINGLETON_BASE CAN_CTRL_1_REG_BASE
#define CAN_SINGLETON_ISRVEC CYGNUM_HAL_INTERRUPT_CAN1_TX
+#define CAN_SINGLETON_TXPRIO CYGNUM_DEVS_CAN_LPC2XXX_CAN0_TX_PRIO
+#define CAN_SINGLETON_RXPRIO CYGNUM_DEVS_CAN_LPC2XXX_CAN0_RX_PRIO
#endif
#ifdef CYGINT_DEVS_CAN_LPC2XXX_CAN1
LPC2XXX_CAN_INFO(lpc2xxx_can1_info, CAN1_FLAG_STARTUP_ACCFILT_SETUP);
#define CAN_CTRL_SINGLETON_BASE CAN_CTRL_2_REG_BASE
#define CAN_SINGLETON_ISRVEC CYGNUM_HAL_INTERRUPT_CAN2_TX
+#define CAN_SINGLETON_TXPRIO CYGNUM_DEVS_CAN_LPC2XXX_CAN1_TX_PRIO
+#define CAN_SINGLETON_RXPRIO CYGNUM_DEVS_CAN_LPC2XXX_CAN1_RX_PRIO
#endif
#ifdef CYGINT_DEVS_CAN_LPC2XXX_CAN2
LPC2XXX_CAN_INFO(lpc2xxx_can2_info, CAN2_FLAG_STARTUP_ACCFILT_SETUP);
#define CAN_CTRL_SINGLETON_BASE CAN_CTRL_3_REG_BASE
#define CAN_SINGLETON_ISRVEC CYGNUM_HAL_INTERRUPT_CAN3_TX
+#define CAN_SINGLETON_TXPRIO CYGNUM_DEVS_CAN_LPC2XXX_CAN2_TX_PRIO
+#define CAN_SINGLETON_RXPRIO CYGNUM_DEVS_CAN_LPC2XXX_CAN2_RX_PRIO
#endif
#ifdef CYGINT_DEVS_CAN_LPC2XXX_CAN3
LPC2XXX_CAN_INFO(lpc2xxx_can3_info, CAN3_FLAG_STARTUP_ACCFILT_SETUP);
#define CAN_CTRL_SINGLETON_BASE CAN_CTRL_4_REG_BASE
#define CAN_SINGLETON_ISRVEC CYGNUM_HAL_INTERRUPT_CAN4_TX
+#define CAN_SINGLETON_TXPRIO CYGNUM_DEVS_CAN_LPC2XXX_CAN3_TX_PRIO
+#define CAN_SINGLETON_RXPRIO CYGNUM_DEVS_CAN_LPC2XXX_CAN3_RX_PRIO
#endif
#endif // #if CYGINT_IO_CAN_CHANNELS > 1
@@ -767,7 +791,7 @@
// Create TX interrupt
//
cyg_drv_interrupt_create(CAN_ISRVEC(info),
- 0, // Priority does not
matter LPC2xxx
+ CAN_TXPRIO(info),
(cyg_addrword_t)chan, // Data item passed to
interrupt handler
lpc2xxx_can_tx_ISR,
lpc2xxx_can_tx_DSR,
@@ -780,7 +804,7 @@
// Create RX interrupt
//
cyg_drv_interrupt_create(CAN_ISRVEC(info) + 6,
- 0, // Priority does not
matter for LPC2xxx
+ CAN_RXPRIO(info),
(cyg_addrword_t)chan, // Data item passed to
interrupt handler
lpc2xxx_can_rx_ISR,
lpc2xxx_can_rx_DSR,
@@ -800,7 +824,7 @@
// Create err interrupt
//
cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_CAN,
- 0, // Priority does
not matter for LPX2xxx
+ CYGNUM_DEVS_CAN_LPC2XXX_PRIO,
0, // Data item passed
to interrupt handler
lpc2xxx_can_err_ISR,
lpc2xxx_can_err_DSR,
--- ChangeLog.orig 2007-07-12 15:19:18.000000000 +0200
+++ ChangeLog 2007-08-17 17:26:56.000000000 +0200
@@ -1,3 +1,8 @@
+2007-08-17 Hans Rosenfeld <[EMAIL PROTECTED]>
+
+ * cdl/i2c_lpc2xxx.cdl, src/i2c_lpc2xxx.c: added option to set
+ interrupt priority
+
2007-07-12 Hans Rosenfeld <[EMAIL PROTECTED]>
* lpc2xxx: driver for on-chip I2C unit
--- cdl/i2c_lpc2xxx.cdl.orig 2007-07-12 15:45:19.000000000 +0200
+++ cdl/i2c_lpc2xxx.cdl 2007-08-17 16:44:46.000000000 +0200
@@ -57,4 +57,16 @@
Philips LPC2xxx controllers."
compile i2c_lpc2xxx.c
+
+ cdl_option CYGNUM_DEVS_I2C_ARM_LPC2XXX_PRIO {
+ display "interrupt priority for I2C interface"
+ parent CYGHWR_HAL_ARM_LPC2XXX_VIC
+ active_if CYGHWR_HAL_ARM_LPC2XXX_VIC
+ flavor data
+ default_value 3
+ legal_values 0 to 16
+ description "The interrupt priority corresponds to the vector
+ number in the Vectored Interrupt Controller. Lower
+ numbers designate higher priorities."
+ }
}
\ No newline at end of file
--- src/i2c_lpc2xxx.c.orig 2007-07-12 15:45:03.000000000 +0200
+++ src/i2c_lpc2xxx.c 2007-08-17 15:10:38.000000000 +0200
@@ -71,6 +71,7 @@
#define I2C_XFER 8
#define I2C_INTR CYGNUM_HAL_INTERRUPT_I2C
+#define I2C_PRIO CYGNUM_DEVS_I2C_ARM_LPC2XXX_PRIO
#define I2C_FREQ (CYGNUM_HAL_ARM_LPC2XXX_CLOCK_SPEED /
CYGNUM_HAL_ARM_LPC2XXX_VPBDIV)
#define I2C_BASE CYGARC_HAL_LPC2XXX_REG_I2_BASE
@@ -260,7 +261,7 @@
cyg_drv_mutex_init(&i2c_lock);
cyg_drv_cond_init(&i2c_wait, &i2c_lock);
cyg_drv_interrupt_create(
- I2C_INTR, 0, (cyg_addrword_t) 0, &i2c_lpc2xxx_isr,
+ I2C_INTR, I2C_PRIO, (cyg_addrword_t) 0, &i2c_lpc2xxx_isr,
&i2c_lpc2xxx_dsr, &i2c_hand, &i2c_data);
cyg_drv_interrupt_attach(i2c_hand);
--- ChangeLog.orig 2007-07-12 15:19:33.000000000 +0200
+++ ChangeLog 2007-08-17 17:32:01.000000000 +0200
@@ -1,3 +1,8 @@
+2007-08-17 Hans Rosenfeld <[EMAIL PROTECTED]>
+
+ * cdl/spi_lpc2xxx.cdl, src/spi_lpc2xxx.cxx: added option to set
+ interrupt priorities
+
2007-07-12 Hans Rosenfeld <[EMAIL PROTECTED]>
* lpc2xxx: driver for on-chip SPI units
--- cdl/spi_lpc2xxx.cdl.orig 2007-07-12 15:48:46.000000000 +0200
+++ cdl/spi_lpc2xxx.cdl 2007-08-17 16:44:40.000000000 +0200
@@ -53,22 +53,46 @@
parent CYGPKG_IO_SPI
active_if CYGPKG_IO_SPI
+ requires CYGPKG_ERROR
include_dir cyg/io
compile spi_lpc2xxx.cxx
- cdl_option CYGPKG_DEVS_SPI_ARM_LPC2XXX_BUS0 {
+ cdl_component CYGPKG_DEVS_SPI_ARM_LPC2XXX_BUS0 {
display "Enable SPI interface 0"
flavor bool
default_value 1
description "The LPC2xxx controllers contain two SPI interfaces.
Enable this option to get support for SPI interface 0."
+
+ cdl_option CYGNUM_DEVS_SPI_ARM_LPC2XXX_BUS0_PRIO {
+ display "Interrupt priority for SPI interface 0"
+ parent CYGHWR_HAL_ARM_LPC2XXX_VIC
+ active_if CYGHWR_HAL_ARM_LPC2XXX_VIC
+ flavor data
+ default_value 1
+ legal_values 0 to 16
+ description "The interrupt priority corresponds to the vector
+ number in the Vectored Interrupt Controller. Lower
+ numbers designate higher priorities."
+ }
}
- cdl_option CYGPKG_DEVS_SPI_ARM_LPC2XXX_BUS1 {
+ cdl_component CYGPKG_DEVS_SPI_ARM_LPC2XXX_BUS1 {
display "Enable SPI interface 1"
flavor bool
default_value 1
description "The LPC2xxx controllers contain two SPI interfaces.
Enable this option to get support for SPI interface 1."
+ cdl_option CYGNUM_DEVS_SPI_ARM_LPC2XXX_BUS1_PRIO {
+ display "Interrupt priority for SPI interface 1"
+ parent CYGHWR_HAL_ARM_LPC2XXX_VIC
+ active_if CYGHWR_HAL_ARM_LPC2XXX_VIC
+ flavor data
+ default_value 2
+ legal_values 0 to 16
+ description "The interrupt priority corresponds to the vector
+ number in the Vectored Interrupt Controller. Lower
+ numbers designate higher priorities."
+ }
}
}
\ No newline at end of file
--- src/spi_lpc2xxx.cxx.orig 2007-07-12 15:49:33.000000000 +0200
+++ src/spi_lpc2xxx.cxx 2007-08-17 15:09:37.000000000 +0200
@@ -303,7 +303,8 @@
*/
void spi_lpc2xxx_init_bus(cyg_spi_lpc2xxx_bus_t *bus,
cyg_addrword_t dev,
- cyg_vector_t vec)
+ cyg_vector_t vec,
+ cyg_priority_t prio)
{
bus->spi_bus.spi_transaction_begin = spi_lpc2xxx_begin;
bus->spi_bus.spi_transaction_transfer = spi_lpc2xxx_transfer;
@@ -319,7 +320,7 @@
bus->spi_dev = (struct spi_dev *) dev;
bus->spi_vect = vec;
cyg_drv_interrupt_create(
- vec, 0, (cyg_addrword_t) bus,
+ vec, prio, (cyg_addrword_t) bus,
&spi_lpc2xxx_isr, &spi_lpc2xxx_dsr,
&bus->spi_hand, &bus->spi_intr);
cyg_drv_interrupt_attach(bus->spi_hand);
@@ -342,7 +343,8 @@
spi_lpc2xxx_init_bus(&cyg_spi_lpc2xxx_bus0,
CYGARC_HAL_LPC2XXX_REG_SPI0_BASE,
- CYGNUM_HAL_INTERRUPT_SPI0);
+ CYGNUM_HAL_INTERRUPT_SPI0,
+ CYGNUM_DEVS_SPI_ARM_LPC2XXX_BUS0_PRIO);
#endif
#ifdef CYGPKG_DEVS_SPI_ARM_LPC2XXX_BUS1
addr = CYGARC_HAL_LPC2XXX_REG_PIN_BASE
@@ -352,7 +354,8 @@
HAL_WRITE_UINT32(addr, tmp);
spi_lpc2xxx_init_bus(&cyg_spi_lpc2xxx_bus1,
CYGARC_HAL_LPC2XXX_REG_SPI1_BASE,
- CYGNUM_HAL_INTERRUPT_SPI1);
+ CYGNUM_HAL_INTERRUPT_SPI1,
+ CYGNUM_DEVS_SPI_ARM_LPC2XXX_BUS1_PRIO);
#endif
}
};
Index: ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/serial/generic/16x5x/current/ChangeLog,v
retrieving revision 1.16
diff -u -r1.16 ChangeLog
--- ChangeLog 22 Jun 2007 11:41:49 -0000 1.16
+++ ChangeLog 17 Aug 2007 17:00:03 -0000
@@ -1,3 +1,9 @@
+2007-08-17 Hans Rosenfeld <[EMAIL PROTECTED]>
+
+ * src/ser_16x5x.c: Added int_prio to pc_serial_info to enable
+ setting of interrupt priority. If unset the default priority is
+ used as before.
+
2007-06-22 Alexander Aganichev <[EMAIL PROTECTED]>
* cdl/ser_generic_16x5x.cdl
Index: src/ser_16x5x.c
===================================================================
RCS file:
/cvs/ecos/ecos/packages/devs/serial/generic/16x5x/current/src/ser_16x5x.c,v
retrieving revision 1.15
diff -u -r1.15 ser_16x5x.c
--- src/ser_16x5x.c 22 Jun 2007 11:41:49 -0000 1.15
+++ src/ser_16x5x.c 17 Aug 2007 17:00:03 -0000
@@ -182,6 +182,7 @@
typedef struct pc_serial_info {
cyg_addrword_t base;
int int_num;
+ int int_prio;
cyg_interrupt serial_interrupt;
cyg_handle_t serial_interrupt_handle;
#ifdef CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO
@@ -375,6 +376,7 @@
if (chan->out_cbuf.len != 0) {
cyg_drv_interrupt_create(ser_chan->int_num,
+ ser_chan->int_prio > 0 ? ser_chan->int_prio :
CYG_IO_SERIAL_GENERIC_16X5X_INT_PRIORITY,
(cyg_addrword_t)chan,
pc_serial_ISR,
Index: ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/serial/arm/lpc2xxx/current/ChangeLog,v
retrieving revision 1.3
diff -u -r1.3 ChangeLog
--- ChangeLog 22 Jun 2007 11:41:49 -0000 1.3
+++ ChangeLog 17 Aug 2007 17:02:26 -0000
@@ -1,3 +1,9 @@
+2007-08-17 Hans Rosenfeld <[EMAIL PROTECTED]>
+
+ * cdl/ser_arm_lpc2xxx.cdl, include/arm_lpc2xxx_ser.inl: Added
+ option to set interrupt priorities. Initialize int_prio field of
+ pc_serial_info.
+
2007-06-22 Alexander Aganichev <[EMAIL PROTECTED]>
* cdl/ser_arm_lpc2xxx.cdl:
Index: cdl/ser_arm_lpc2xxx.cdl
===================================================================
RCS file:
/cvs/ecos/ecos/packages/devs/serial/arm/lpc2xxx/current/cdl/ser_arm_lpc2xxx.cdl,v
retrieving revision 1.2
diff -u -r1.2 ser_arm_lpc2xxx.cdl
--- cdl/ser_arm_lpc2xxx.cdl 22 Jun 2007 11:41:49 -0000 1.2
+++ cdl/ser_arm_lpc2xxx.cdl 17 Aug 2007 17:02:26 -0000
@@ -91,6 +91,18 @@
This option includes the serial device driver for the ARM
LPC2XXX port 0."
+ cdl_option CYGNUM_IO_SERIAL_ARM_LPC2XXX_SERIAL0_PRIO {
+ display "interrupt priority for serial port 0"
+ parent CYGHWR_HAL_ARM_LPC2XXX_VIC
+ active_if CYGHWR_HAL_ARM_LPC2XXX_VIC
+ flavor data
+ default_value 4
+ legal_values 0 to 16
+ description "The interrupt priority corresponds to the vector
+ number in the Vectored Interrupt Controller. Lower
+ numbers designate higher priorities."
+ }
+
cdl_option CYGDAT_IO_SERIAL_ARM_LPC2XXX_SERIAL0_NAME {
display "Device name for ARM LPC2XXX serial port 0 driver"
flavor data
@@ -136,6 +148,18 @@
This option includes the serial device driver for the ARM
LPC2XXX port 1."
+ cdl_option CYGNUM_IO_SERIAL_ARM_LPC2XXX_SERIAL1_PRIO {
+ display "interrupt priority for serial port 1"
+ parent CYGHWR_HAL_ARM_LPC2XXX_VIC
+ active_if CYGHWR_HAL_ARM_LPC2XXX_VIC
+ flavor data
+ default_value 5
+ legal_values 0 to 16
+ description "The interrupt priority corresponds to the vector
+ number in the Vectored Interrupt Controller. Lower
+ numbers designate higher priorities."
+ }
+
cdl_option CYGDAT_IO_SERIAL_ARM_LPC2XXX_SERIAL1_NAME {
display "Device name for ARM LPC2XXX serial port 1 driver"
flavor data
Index: include/arm_lpc2xxx_ser.inl
===================================================================
RCS file:
/cvs/ecos/ecos/packages/devs/serial/arm/lpc2xxx/current/include/arm_lpc2xxx_ser.inl,v
retrieving revision 1.2
diff -u -r1.2 arm_lpc2xxx_ser.inl
--- include/arm_lpc2xxx_ser.inl 15 Nov 2004 09:20:27 -0000 1.2
+++ include/arm_lpc2xxx_ser.inl 17 Aug 2007 17:02:27 -0000
@@ -87,7 +87,8 @@
#ifdef CYGPKG_IO_SERIAL_ARM_LPC2XXX_SERIAL0
static pc_serial_info lpc2xxx_serial_info0 =
{ CYGARC_HAL_LPC2XXX_REG_UART0_BASE,
- CYGNUM_HAL_INTERRUPT_UART0
+ CYGNUM_HAL_INTERRUPT_UART0,
+ CYGNUM_IO_SERIAL_ARM_LPC2XXX_SERIAL0_PRIO
};
#if CYGNUM_IO_SERIAL_ARM_LPC2XXX_SERIAL0_BUFSIZE > 0
@@ -135,7 +136,8 @@
#ifdef CYGPKG_IO_SERIAL_ARM_LPC2XXX_SERIAL1
static pc_serial_info lpc2xxx_serial_info1 =
{ CYGARC_HAL_LPC2XXX_REG_UART1_BASE,
- CYGNUM_HAL_INTERRUPT_UART1
+ CYGNUM_HAL_INTERRUPT_UART1,
+ CYGNUM_IO_SERIAL_ARM_LPC2XXX_SERIAL1_PRIO
};
#if CYGNUM_IO_SERIAL_ARM_LPC2XXX_SERIAL1_BUFSIZE > 0
static unsigned char
Index: ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/eth/ns/dp83902a/current/ChangeLog,v
retrieving revision 1.11
diff -u -r1.11 ChangeLog
--- ChangeLog 12 Aug 2004 13:01:17 -0000 1.11
+++ ChangeLog 17 Aug 2007 16:57:33 -0000
@@ -1,3 +1,8 @@
+2007-08-17 Hans Rosenfeld <[EMAIL PROTECTED]>
+
+ * src/if_dp83902a.c, include/dp83902a.h: HW-specific code can
+ define CYGNUM_DEVS_ETH_NS_DP83902A_PRIO to set interrupt priority.
+
2004-08-12 Jani Monoses <[EMAIL PROTECTED]>
* src/if_dp83902a.c: Fix builing with lwip.
Index: include/dp83902a.h
===================================================================
RCS file:
/cvs/ecos/ecos/packages/devs/eth/ns/dp83902a/current/include/dp83902a.h,v
retrieving revision 1.5
diff -u -r1.5 dp83902a.h
--- include/dp83902a.h 23 May 2002 23:00:46 -0000 1.5
+++ include/dp83902a.h 17 Aug 2007 16:57:34 -0000
@@ -185,6 +185,10 @@
// ------------------------------------------------------------------------
// Macros allowing platform to customize some of the driver details
+#ifndef CYGNUM_DEVS_ETH_NS_DP83902A_PRIO
+# define CYGNUM_DEVS_ETH_NS_DP83902A_PRIO 0
+#endif
+
#ifndef CYGHWR_NS_DP83902A_PLF_RESET
# define CYGHWR_NS_DP83902A_PLF_RESET(_b_) do { } while (0)
#endif
Index: src/if_dp83902a.c
===================================================================
RCS file:
/cvs/ecos/ecos/packages/devs/eth/ns/dp83902a/current/src/if_dp83902a.c,v
retrieving revision 1.10
diff -u -r1.10 if_dp83902a.c
--- src/if_dp83902a.c 12 Aug 2004 13:01:17 -0000 1.10
+++ src/if_dp83902a.c 17 Aug 2007 16:57:34 -0000
@@ -178,7 +178,7 @@
#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
cyg_drv_interrupt_create(
dp->interrupt,
- 0, // Priority - unused
+ CYGNUM_DEVS_ETH_NS_DP83902A_PRIO,
(cyg_addrword_t)dp,// Data item passed to ISR & DSR
dp83902a_isr, // ISR
dp83902a_dsr, // DSR
Index: hal_arm_lpc2xxx.cdl
===================================================================
RCS file:
/cvs/ecos/ecos/packages/hal/arm/lpc2xxx/var/current/cdl/hal_arm_lpc2xxx.cdl,v
retrieving revision 1.4
diff -u -r1.4 hal_arm_lpc2xxx.cdl
--- hal_arm_lpc2xxx.cdl 30 Jul 2007 18:09:47 -0000 1.4
+++ hal_arm_lpc2xxx.cdl 17 Aug 2007 15:40:10 -0000
@@ -157,6 +157,29 @@
same as the processor clock."
}
+ cdl_component CYGHWR_HAL_ARM_LPC2XXX_VIC {
+ display "Vectored Interrupt Controller"
+ flavor bool
+ calculated 1
+ description "
+ This option enables or disables the Vectored Interrupt Controller.
+ The LPC2xxx eCos HAL supports up to 17 interrupt levels.
+ Interrupt levels 0 - 15 are vectored IRQs. Vectored IRQs
+ have a higher priority then non vectored IRQs and they
+ are processed faster. Non vectored IRQs are all chained together
+ into one single slot and the ISR need to find out which interrupt
+ occured."
+
+ cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY {
+ display "Default priority for system clock interrupts"
+ flavor data
+ legal_values { 0 to 16 }
+ default_value 0
+ description "The default value for the system clock interrupts is
0 -
+ this is the highest priority IRQ."
+ }
+ }
+
cdl_component CYGNUM_HAL_RTC_CONSTANTS {
display "Real-time clock constants"
flavor none
@@ -206,20 +229,4 @@
debugging via JTAG, as stopping the clock can prevent the
debugger getting control of the system."
}
-
- cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY {
- display "Default priority for system clock interrupts"
- flavor data
- legal_values { 0 to 16 }
- default_value 0
- description "
- The LPC2xxx eCos HAL supports up to 17 interrupt levels.
- Interrupt levels 0 - 15 are vectored IRQs. Vectored IRQs
- have a higher priority then non vectored IRQs and they
- are processed faster. Non vectored IRQs are all chained together
- into one single slot and the ISR need to find out which interrupt
- occured. The default value for the system clock interrupts is 0 -
- this is the highest priority IRQ."
- }
-
}
Index: ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/lpc2xxx/var/current/ChangeLog,v
retrieving revision 1.7
diff -u -r1.7 ChangeLog
--- ChangeLog 30 Jul 2007 18:09:47 -0000 1.7
+++ ChangeLog 17 Aug 2007 15:58:09 -0000
@@ -1,3 +1,8 @@
+2007-08-17 Hans Rosenfeld <[EMAIL PROTECTED]>
+
+ * cdl/hal_arm_lpc2xxx.cdl: added VIC component to support
+ configuration of individual interrupt priorities
+
2007_07-10 Uwe Kindler <[EMAIL PROTECTED]>
* cdl/hal_arm_lpc2xxx.cdl: Added option
