Index: ChangeLog =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/arm9/var/current/ChangeLog,v retrieving revision 1.9 diff -u -r1.9 ChangeLog --- ChangeLog 29 Jan 2009 17:48:56 -0000 1.9 +++ ChangeLog 13 Feb 2009 12:58:46 -0000 @@ -1,3 +1,17 @@ +2009-02-13 Lars Povlsen + + * include/hal_cache.h: Added dummy + HAL_FLASH_CACHES_OFF()/HAL_FLASH_CACHES_ON() macros guarded by + CYGSEM_HAL_FLASH_CACHES_NODISABLE to allow cache operation while + programming flash. Parameterized HAL_DCACHE_SIZE and HAL_ICACHE_SIZE. + Added HAL_DCACHE_STORE(), HAL_DCACHE_INVALIDATE(), and + HAL_DCACHE_FLUSH() macros. Not setting the M-bit (MMU enable) + in HAL_ICACHE_ENABLE(). + + * cdl/hal_arm_arm9.cdl: Added CYGNUM_HAL_ARM_ARM9_DCACHE_SIZE and + CYGNUM_HAL_ARM_ARM9_ICACHE_SIZE options for controlling the actual + hardware's cache sizes. + 2006-02-17 Tom Chase * include/hal_cache.h: Added support for ARM926EJ. Changed Index: cdl/hal_arm_arm9.cdl =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/arm9/var/current/cdl/hal_arm_arm9.cdl,v retrieving revision 1.6 diff -u -r1.6 hal_arm_arm9.cdl --- cdl/hal_arm_arm9.cdl 29 Jan 2009 17:48:56 -0000 1.6 +++ cdl/hal_arm_arm9.cdl 13 Feb 2009 12:58:46 -0000 @@ -106,15 +106,43 @@ write buffer and an MMU." } - cdl_option CYGPKG_HAL_ARM_ARM9_ARM926EJ { + cdl_component CYGPKG_HAL_ARM_ARM9_ARM926EJ { display "ARM ARM926EJ microprocessor" implements CYGINT_HAL_ARM_ARM9_VARIANT default_value 0 no_define define -file=system.h CYGPKG_HAL_ARM_ARM9_ARM926EJ description " - The ARM926EJ has 16k data cache, 16k instruction cache, 16 word + The ARM926EJ has by default 8k data cache, 16k instruction cache, 16 word write buffer and an MMU." + + + cdl_option CYGNUM_HAL_ARM_ARM9_DCACHE_SIZE { + display "Data cache size" + flavor data + legal_values 0x1000 to 0x8000 + default_value 0x2000 + active_if CYGINT_HAL_ARM_ARM9_VARIANT == CYGPKG_HAL_ARM_ARM9_ARM926EJ + no_define + define HAL_DCACHE_SIZE + description " + This size of the data cache for this particular + ARM926-based processor." + } + + cdl_option CYGNUM_HAL_ARM_ARM9_ICACHE_SIZE { + display "Instruction cache size" + flavor data + active_if CYGINT_HAL_ARM_ARM9_VARIANT == CYGPKG_HAL_ARM_ARM9_ARM926EJ + legal_values 0x1000 to 0x8000 + default_value 0x4000 + no_define + define HAL_ICACHE_SIZE + description " + This size of the instruction cache for this particular + ARM926-based processor." + } + } cdl_option CYGPKG_HAL_ARM_ARM9_ARM940T { Index: include/hal_cache.h =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/arm/arm9/var/current/include/hal_cache.h,v retrieving revision 1.9 diff -u -r1.9 hal_cache.h --- include/hal_cache.h 29 Jan 2009 17:48:56 -0000 1.9 +++ include/hal_cache.h 13 Feb 2009 12:58:47 -0000 @@ -116,12 +116,12 @@ # define CYGHWR_HAL_ARM_ARM9_ALT_CLEAN_DCACHE #elif defined(CYGPKG_HAL_ARM_ARM9_ARM926EJ) -# define HAL_ICACHE_SIZE 0x4000 +/* HAL_ICACHE_SIZE comes from pkgconf/hal_arm_arm9.h. Defaults to 0x4000. */ # define HAL_ICACHE_LINE_SIZE 32 # define HAL_ICACHE_WAYS 4 # define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) -# define HAL_DCACHE_SIZE 0x2000 +/* HAL_DCACHE_SIZE comes from pkgconf/hal_arm_arm9.h. Defaults to 0x2000. */ # define HAL_DCACHE_LINE_SIZE 32 # define HAL_DCACHE_WAYS 4 # define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) @@ -130,6 +130,57 @@ #define CYGHWR_HAL_ARM_ARM926EJ_CLEAN_DCACHE //has instruction to clean D-cache +/* + * Invalidate cache lines in the given range without writing to memory. + */ +#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \ +CYG_MACRO_START \ + register int addr, enda; \ + for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_), \ + enda = (int)(_base_) + (_size_); \ + addr < enda ; \ + addr += HAL_DCACHE_LINE_SIZE ) \ + { \ + asm volatile ( \ + "mcr p15,0,%0,c7,c6,1;" /* flush entry away */ \ + : \ + : "r"(addr) \ + : "memory" \ + ); \ + } \ + asm volatile ( "mcr p15,0,%0,cr7,cr10,4" : : "r" (0) ); /* Drain writebuffer */ \ +CYG_MACRO_END + +/* + * Write dirty cache lines to memory for the given address range. + */ +#define HAL_DCACHE_STORE( _base_ , _size_ ) \ +CYG_MACRO_START \ + register int addr, enda; \ + for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_), \ + enda = (int)(_base_) + (_size_); \ + addr < enda ; \ + addr += HAL_DCACHE_LINE_SIZE ) \ + { \ + asm volatile ("mcr p15,0,%0,c7,c10,1;" /* push entry to RAM */ \ + : \ + : "r"(addr) \ + : "memory" \ + ); \ + } \ + asm volatile ( "mcr p15,0,%0,cr7,cr10,4" : : "r" (0) ); /* Drain writebuffer */ \ +CYG_MACRO_END + +/* + * Write dirty cache lines to memory and invalidate the cache entries + * for the given address range. + */ +#define HAL_DCACHE_FLUSH( _base_ , _size_ ) \ +CYG_MACRO_START \ + HAL_DCACHE_STORE( _base_ , _size_ ); \ + HAL_DCACHE_INVALIDATE( _base_ , _size_ ); \ +CYG_MACRO_END + #elif defined(CYGPKG_HAL_ARM_ARM9_ARM940T) # define HAL_ICACHE_SIZE 0x1000 # define HAL_ICACHE_LINE_SIZE 16 @@ -184,8 +235,8 @@ asm volatile ( \ "mrc p15,0,r1,c1,c0,0;" \ "orr r1,r1,#0x1000;" \ - "orr r1,r1,#0x0003;" /* enable ICache (also ensures */ \ - /* that MMU and alignment faults */ \ + "orr r1,r1,#0x0002;" /* enable ICache (also ensures */ \ + /* that alignment faults */ \ /* are enabled) */ \ "mcr p15,0,r1,c1,c0,0" \ : \ @@ -311,8 +362,8 @@ "bic r1,r1,#0x000C;" /* disable DCache AND write buffer */ \ /* but not MMU and alignment faults */ \ "mcr p15,0,r1,c1,c0,0;" \ - "mov r1,#0;" \ - "mcr p15,0,r1,c7,c6,0" /* clear data cache */ \ + "mov r1,#0;" \ + "mcr p15,0,r1,c7,c6,0" /* invalidate data cache */ \ : \ : \ : "r1" /* Clobber list */ \ @@ -525,6 +576,7 @@ // Cache controls for safely disabling/reenabling caches around execution // of relocated code. +#if !defined(CYGSEM_HAL_FLASH_CACHES_NODISABLE) || !CYGSEM_HAL_FLASH_CACHES_NODISABLE #define HAL_FLASH_CACHES_OFF(_d_, _i_) \ CYG_MACRO_START \ HAL_ICACHE_IS_ENABLED(_i_); \ @@ -541,7 +593,19 @@ if (_d_) HAL_DCACHE_ENABLE(); \ if (_i_) HAL_ICACHE_ENABLE(); \ CYG_MACRO_END +#else /* CYGSEM_HAL_FLASH_CACHES_NODISABLE */ + +#define HAL_FLASH_CACHES_OFF(_d_, _i_) \ + CYG_MACRO_START \ + _d_ = 0; /* avoids warning */ \ + _i_ = 0; /* avoids warning */ \ + CYG_MACRO_END + +#define HAL_FLASH_CACHES_ON(_d_, _i_) \ + CYG_MACRO_START \ + CYG_MACRO_END +#endif /* CYGSEM_HAL_FLASH_CACHES_NODISABLE */ //----------------------------------------------------------------------------- // Virtual<->Physical translations #ifndef HAL_VIRT_TO_PHYS_ADDRESS